ADS8363 Unable to read back registers in Special Mode IV

Hi Jose,

I was able to solve the problem outlined in my original post, but I have an additional question.

Currently I have both the sequencer and FIFO enabled, special read is enabled, and the sequencer length set to 4. I first send a CONVST pulse, which causes the ADS8363 to bring BUSY high for each conversion or for the entire sequence, depending on the value of S[1:0]. Then I send a single RD pulse to read back all 8 channels through SDOA. This works fine.

However, I'd like to speed the process up by beginning the read process while the later channels are being converted. The datasheet warns against doing this on page 24:

The FIFO can be used independently from the sequencer. When both are used, the complete sequence must be finished before reading the data out of the FIFO; otherwise, the data may be corrupted. [emphasis mine]

I therefore tried disabling the FIFO so that I could read the sequence while conversion is ongoing without corrupting the data. First I tested what would happen if I do wait for the BUSY signal to fall before reading the results. Unfortunately, this results in only the first 2 channels being read back rather than 8, even though BUSY signal indicates that it's converting all 8. If I try sending multiple RD pulses in a row (without CONVST) the same first 2 channels are read back every time. Page 24 of the ADS8363 datasheet (Rev B) states:

The ADS8363/7363/7223 feature a programmable sequencer that controls the switching of the ADC input multiplexer in pseudo-differential, automatic channel-selection mode only. When used, a single read pulse allows reading of all stored conversion data.

Note that there's no mention of the FIFO yet, just the sequencer. I took this to mean that by setting Sequencer Mode S[1:0] to 0b11 and Sequencer Length SL[1:0] to 0b11 that I could convert all 8 channels with a single CONVST pulse and read all 8 channels with a single RD pulse. This does not seem to be true.

Is it possible to send a single RD pulse to read all 8 channels before the last channels are finished being sampled? (timed such that those channels will have been sampled by the time the results are read out)

Correct me if I've misunderstood:

If I were to use Mode III to read from SDOA and SDOB simultaneously, I can set S[1:0] to 0b11 and SL[1:0] to 0b11 without enabling the FIFO. Therefore, I will be able to use a single CONVST pulse to convert all 8 channels, and then use a single RD pulse before the last channel has finished converting to read back all 8 channels. (I'm assuming this is now possible due to the FIFO being disabled)

If this is true, would you recommend I set S[1:0] to 0b10 instead of 0b11 so that I send the RD pulse after the ADC momentarily brings BUSY low? Like so:

1. Pulse CONVST while providing clock signal to ADC

2. BUSY line will go high

3. When BUSY line momentarily goes low, pulse RD. BUSY will go high again and continue to dip when each conversion finishes, but the MCU won't care

4. Read 4 channels' worth of information in sequence per SDO line (8 combined).