I'm confused about the operation of the pulse mode. In the May 2015 datasheet,
page 15 says: "The SYNC input synchronizes the output signal to a known time reference. In sine mode, SYNC resets the sine wave to the zero crossing. In Pulse mode, SYNC selects one of two user-programmed dc levels."
On page 23, 8.2.7.1 says: "In sine, dc, and pulse mode, SW/TD controls the output switch. When SW/TD is low, all switches are forced open, overriding the switch register setting (SW[2:0]). When SW/TD is high, the switch is transparent to the value of register setting. In power-down mode, the switch is forced open."
And page 25 further describes pulse operation: "In pulse mode, the SYNC pin selects one of two pre-programmed pulse levels. The pulse levels are programmable from +2.5 V to –2.5 V in approximately 3-dB steps by pulse level registers PULSA and PULSB. When SYNC is low, the value of the PULSA register drives the DAC; when SYNC is high, the value of the PULSB register is the code of the DAC, as shown in Figure 41. When the SYNC pin is changed, the DAC output updates immediately to the new code."
Does the pulse mode pattern (A or B) change one clock after the SYNC pulse changes state or according to the divide by 16 clock sync timing shown in figure 39?
If I want to feed the DAC pulse outputs through the switch as shown in figure 51, would the switch configuration change from open to closed one clock after SW/TD changes goes high or 1 to 16 clocks after SW/TD goes high (depending on sync as shown in figure 39)?
