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ADS1231 Low number of samples

Other Parts Discussed in Thread: ADS1231, ADS1231REF

Hello

I am using ADS1231 for a weigh scale application.

I implemented a bit banged approach to achieve 24 bit data, plus one clock to keep Dout pin high, till next sample is retrieved.

Although the PDWN is high suggesting 80 samples/second, i get only average 17/18 samples per second.

I have no problem in reading correct data ,  i am able to achieve very high resolution.

Can someone help me out here? I will provide more info if someone can help.

  • Here is the piece of code which i wrote .

    void adc_measure()
    {
    	        weight_raw = 0;
    		
    		while((dout_GetVal()));//wait till ADC isn't ready
    	
    		for(adc_counts = 0;adc_counts < 24;adc_counts++)
    		{
    			sck_SetVal();					//set the clock pin
    			WAIT1_Waitus(900);				//wait for 900uSec
    			weight_raw <<= 1;				//left shift data by 1 
    			sck_ClrVal();					//clear clock pin
    			if((dout_GetVal()) == 1)weight_raw++;//if the value on pin is high then inc value by 1
    		}
    		sck_SetVal();//25th pulse
    		WAIT1_Waitus(950);	
    		sck_ClrVal();		
    		
    		if(weight_raw & 0x800000) weight_raw = 0;		
    							
    		temp_adc_val = weight_raw;
    		
    }			

    The SPEED pin = 1 for 80sps,

    PDWN = 1

    The sampling rate practically which i get is 12.5 samples per second.

    If i remove the 

    WAIT1_Waitus(900);	 

    I get flawed readings.

    The adc_measure() is constantly called from main()

    Am i doing something wrong here?

  • Hi Abhijit,

    If you are converting at 80 sps, then the data will be available every 12.5ms.  In your loop, waiting the 900us high time for each SCLK period is (900us *24 bits) equal to 21.6ms.  It is not possible given those conditions to reach the data output rate.

    When you comment out the wait time, you are basically running the SCLK at an unknown rate based solely on the length of time it takes to process the command sequence.  You need to adjust the SCLK period so that it follows Figure 19 on page 12 of the ADS1231 datasheet and that the total length of time to read the data is less than the data output rate.  Notice that the tSCLK high or low times must be at least 100ns.  This means that the total time for one completed SCLK cycle must be at least 200ns period.  So the fastest SCLK frequency is 5MHz.  It can be slower, but you must be at least fast enough to read the entire result.

    Also notice that there is a tUPDATE period.  This is the time where the next conversion results are updated.  If you are reading through this period, your results will be corrupted with a mix of old and new results.

    It is best to monitor your SPI signal lines with a scope or logic analyzer to make sure you are meeting all the timing requirements.  Mostly likely you will need some delay both high and low time to ensure that you meet the 100ns specification for both low and high times for SCLK. 1us delay should be sufficient to read the results.  So try changing the 900 to 1, and then add the same statement after sck_ClrVal().

    Best regards,

    Bob B

  • Dear Bob

    Thanks for replying. Appreciated.

    I have tried all delays ,ranging from the mandatory 150ns and till 900us. Only 900us time gives me constant and precise reads.

    All other times gives out unstable reads. On a DSO I see that the ADCmeasure function takes 80ms time as opposed to 22ms as calculated

  • Hi Abhijit,

    My calculation was based on the assumption that the 900us was the slowest part of the clocking system.  Apparently your micro processor clock speed is very slow.  If you have the ADS1231 set to 80sps, and it takes you longer than 12.5ms to read the data, then you are violating the timing for the device if it takes 80ms to read out the data.  Set the data rate to 10sps (100ms) period where you can read the data completely before the next result becomes available if it takes 80ms to read out the results.

    Best regards,

    Bob B

  • Hi Bob

    I am operating at 20Mhz.I think that's fast enough.

    How much should be the bus freq according to your assumption?

    I need 80 samples in a second.

  • I tried various bus frequencies till 80mhz.
    Still same issue.
    FYI I am using a cortex m4 mcu
  • Where are you Bob?

  • Hi Abhijit,

    I'm in the US and we generally don't work over the weekend to answer questions.  As to your particular situation, how are you verifying your clock timing?  If you change the clock speed by four, then you should see a four time increase in your communication.  If you do not see this increase, then there must be something wrong in your configuration or with portions of your code related to changing your GPIO.

    Can you send me your schematic and screen shots of the communication showing CS, SCLK and DOUT/DRDY?  I want to make sure I fully understand what is going on with the communication.

    Thanks,

    Bob B

  • Dear Bob

    Thanks for replying, and i almost forgot the timezone :)

    Although please find the working configuration screen shots and my ADC schematic attached.

    Please notice that DRDY/DOUT time from low going edge to the next low going edge is 58ms.

    In my code i have a 931us delay between SCK pulses which you can see in the SCK image.

    I have shared my ADC schematic part as pdf.

    Please get back if you find something  schematic-power.pdf

  •    Dear Bob

    Now i have changed time between SCK to 1us.

    Here it doesn't measure correct

    Count varies from 108748 to 107778, from 259 uV to 256 uV (rather randomly in last 4 digits or 23uV )

    This also crosses 117440 or 280 uV

    Delay of 900us will resolve better , with all digits stable (as you can see in the last post)

    Although here the count is 114687 or 273 uV

    Am i doing something wrong?

  • Hi Abhijit,

    Let's start with the schematic.  Your DVDD for the ADS1231 is at 5V, but your microprocessor is running at 3.3V.  This means the micro must be capable of tolerating a 5V input (and most are not that I'm aware of) and the ADS1231 is only seeing at best 3.3V for a logic high.  With a 5V digital logic for the ADS1231, the logic level for VIH as specified in the electrical characteristics table on page 3 of the datasheet is 0.8DVDD (4V).  This is not reliable and the ADS1231 digital voltage should match the micro.  You do not need the same voltage for AVDD and DVDD for the ADS1231, so I would suggest that you connect DVDD to the 3.3V_MCU supply.

    However, the grounds for the ADS1231 should be at the same potential.  Any added inductance, including long trace lengths, between AGND and DGND of the ADS1231 has the potential for damaging the device.

    Now let's discuss the screen shots you sent.  You may think you are getting stable readings by adding the 900us delay, but what you are actually receiving is invalid readings by violating the timing specifications.  Notice on page 13 and Figure 19 of the ADS1231 datasheet that there is a tUPDATE period that takes place at the end of every conversion cycle.  At 80sps, the period is 1/80 or 12.5ms.  Also notice that in the table below the figure is a description for tUPDATE that states "Data updating: no readback allowed". If you roughly calculate that one SCLK cycle takes 1ms, and you issue 25 SCLKs, then the period for one complete read out of the data takes 25ms.  This means that you are attempting to read through the update period which is "not allowed".  So even though your reading may be stable, they are invalid.

    So now we move on to the unstable readings.  First review the noise performance table on page 6 of the datasheet.  You will see that at 80sps and 5V AVDD that the best noise performance is 15.9 bits noise free.  This performance is measured with shorted inputs at mid-AVDD supply (so that the inputs remain at the correct common-mode input range).  In other words, you will not see stable readings and in fact the last 8 bits will be fluctuating.  At 5V AVDD this amounts to typically 622.1nV peak to peak of noise for the ADS1231.

    One other thing I want to cover is your calculation.  The full-scale range for the ADS1231 is +/- 0.5VREF/128, or VREF/128.  The LSB value (one code) is FSR/(2^24-1). So the value of one code is the (VREF/128)/(2^24-1) and is approximately 2.33nV.  Based on the typical noise of 622.1nV, the code variation is about 267 codes or approximately 8.1 bits.

    I'm not quite sure how you are deriving your voltages, but they seem a little high.  I think in the end that you are seeing anywhere from 3 to 10 times the normal noise and perhaps more.  The noise can come from a variety of different noise sources including power line cycle noise.  The first thing to do is to make sure that you can achieve the shorted input noise performance.  If you cannot, then you need to investigate possible issues with your supplies and board layout.  You should have a very good ground plane area at least around the analog portions and the ADS1231.  You have very little analog input filtering, and it also appears that the common-mode caps are the same value as the differential cap.  The differential cap must be at least 10 times greater in value as compared to the common-mode caps to lower noise and drift issues.  You may also want to add some series resistance in series with the analog inputs and before the capacitors to help lower external noise.

    I also see that you have a relay in your schematic.  Relays can be a very troublesome noise issue as activation can cause considerable ground bounce and supply instability.

    So to recap what I have stated, you cannot use the 900us delay on SCLK as this violates the timing specification for 80sps.  You should make the ADS1231 DVDD supply match the micro supply so that the digital circuits are getting the proper voltage, and lastly noise is to be expected but excessive noise must be eliminated and the bulk of the noise is most likely coming from external sources.

    Best regards,

    Bob B

  • Dear Bob

    Foremost I would like to thank you for such a comprehensive post.

    I will try all things mentioned and get back.

    Although few things , I will clear.

    My MCU is 5v tolerant.

    I have solid ground plane covering analog section.

  • Hi Abhijit,

    Even though your micro is 5V tolerant, the ADS1231 VIH minimum is DVDD*0.8 which is 4V when DVDD is 5V.  If the micro supply is 3.3V, then the output of the micro can be no more than 3.3V which is below the specified minimum for the ADS1231 digital inputs and the system may not be reliable in all operational cases.

    Best regards,

    Bob B

  • Hello Bob

    I tried all things that you have mentioned.

    There is no improvement at all.

  • Forgot to mention
    Shorted input noise performance is spot on.
    I get 0
  • Hi Abhijit,

    You said you shorted the inputs and 'get 0'.  First of all, how did you short the inputs and did you still have a valid reference.  Shorted input test should have a resistor divider with two equal value resistors (10k ohm for example) connected between AVDD and AGND.  Where the two resistors come together, you connect both inputs so that the inputs are shorted together at mid-AVDD supply to place the short within the proper common-mode for the ADS1231 input.  If you do this and you have also applied a valid reference voltage (the same as you have been using...the AVDD supply) you most likely will not see 0 code output.  There will be some ADC offset and noise.  This should be near 0, but definitely not holding a steady value.  The range in noise should follow what I stated a few posts earlier.

    If you send me a minimum of 128 successive returned values, we can establish the level of noise and see if you meet the shorted noise tests.  If you are seeing a steady '0' then something is wrong either with communication or setup of the ADC.

    To help with diagnosis, you need to tell me exactly what you did and then associate a series of at least 128 data points of continuous data.  For example, take a series of readings and save the data.  Add some series resistance (1 to 2K for example) to the analog inputs prior to the caps and collect some more data.  In the end you need to determine the source of your noise and how best to reduce the effects of the noise on the measurement.

    You must also make sure that all the timing requirements and digital voltages to the digital inputs that I have previously discussed have been met.  For example, the PDWN pin must be greater than 4V if DVDD is 5V for the ADS1231.  If the micro is powered by 3.3V, then the ADS1231 DVDD supply should also be powered by 3.3V.

    Best regards,

    Bob B

  • Hi Bob

    Thanks for replying. I appreciate your patience with me :)

    I was not taking shorted input test as you have mentioned. Apology for that.

    I corrected the setup as per your suggestion.

    I took 2 tests , 

    1) Shorted input test should have a resistor divider with two equal value resistors (10k ohm for example) connected between AVDD and AGND.  Where the two resistors come together, you connect both inputs so that the inputs are shorted together at mid-AVDD supply to place the short within the proper common-mode for the ADS1231input

    2) Add some series resistance (1K ) to the analog inputs prior to the caps and collect some more data (Both analog inputs were shorted together before connecting to 2.5v)

    I have attached the file to this post.

    3) You must also make sure that all the timing requirements and digital voltages to the digital inputs that I have previously discussed have been met.  For example, the PDWN pin must be greater than 4V if DVDD is 5V for the ADS1231.  If the micro is powered by 3.3V, then the ADS1231 DVDD supply should also be powered by 3.3V

    Ensured this by connecting DVDD to 3.3v

    drop.xlsx

  • Hi Abhijit,

    The shorted input tests appear normal.  There is a slight negative offset (not unusual) and the code variation is within expectations for peak to peak noise.  When you connect the load cell you should get similar results.  With no weight on the load cell the output should be near zero or in a balanced state (similar to the shorted case).  If you repeat the same measurements you should get similar results.  If they are much noisier, then noise is getting into the measurement path.  Usually this is EMI/RFI and/or power line cycle noise.  Any noise from nearby motors or where high switching currents are taking place can enter the cabling that acts as an antenna.

    Best regards,

    Bob B

  • I am having a high fever few days , so couldn't reply. Apology.

    So you are saying that this is how the ADC will measure?

    For a 1kg load which I calibrated , I get variation within 5 to 10 grams.

    This shouldn't be the case I believe.

  • Hi Abhijit,

    What I said is the shorted input noise is the best possible resolution.  In other words you will never get a more stable reading with a direct measurement.  Based on your initial data you have much greater noise in your system apart from ADC noise.

    Your resolution in grams will be determined by a ratio of full-scale output of the load cell to the full-scale range of the ADC.  Noise-free counts refers to the total counts available based on the noise-free resolution of the converter.  With 5V excitation, the full-scale range of the ADC is about 39mV.  If the load cell has a capacity of 2mV/V, then with 5V excitation the full-scale output of the load cell is 10mV.  The noise-free bits for the ADC at 5V and 80sps is 15.9 bits.

    Calculating for noise-free counts you take the ratio of load cell output and ADC full-scale range and multiply times the total number of noise-free bits [(10mV/39mV)*2^15.9] which equates to about 15,678 counts.  For a 1kg output your scale resolution is full-scale divided by the number of noise-free counts (1kg/15678) which is about 0.064 gram resolution.  This is best case based on shorted input noise.  If you are only able to achieve 5-10 gram resolution, then you need to discover the source of your noise and eliminate it from the ADC input so that the noise does not become a part of the measurement.  Remember that any external noise is gained by 128.  I stated some of the sources of external noise in an earlier post.

    Best regards,

    Bob B

  •  Hello Bob

    These days i was building a new board taking suggestions from you and from ADS1231REF board.

    It took a while!

    I populated and tested , and this time results are better and as expected.

    Although one thing i cannot duplicate from the ADS1131REF board.

    I have populated NFM21PC105F1C3D capacitors between all digital signals and to VREF,AVDD and AINP, AINN.

    When my MCU send SCLK , the signal gets shunted.

    So, i don't get any readings for SCLK,SDA through these capacitors.

    Why is this so?

  • Hi Abhijit,

    The digital filters should be a different value.  This is more clear if you look at the BOM in the ADS1131REF user's guide.  What is happening is the 1uF filter cap is filtering out the digital signals.  What is used on the REF board is NFM21CC101U1H3D which is 100pF.  This will filter out the higher frequency components like EMI/RFI but still allow the lower speed signals like SCLK to pass.

    Best regards,

    Bob B

  • Hello Bob

    I am extremely grateful for your patient support during our entire conversation.

    This one is so silly and amateur of me, thanks for pointing that out.

    I will check with these capacitors.

    Meanwhile thanks once again!!