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[ DAC6311 ] Serial Interface with Open Drain output

Other Parts Discussed in Thread: DAC6311

[ DAC6311 ] Serial Interface with Open Drain output

Adding information with red.

 Correction with valid description in blue

Hi,

My customer has evaluated DAC6311 connecting with open drain interface with 10kohm pull-up.
However, from its slow input waveform, it's obvious that 10kohm resistor is not best value.

Do you have any of guidelines of selecting pull up resistor value for DAC6311 in conjunction with open drain output?

AVDD/VREF = 2.6V
Pull-Up voltage via 10kohm = 2.6V




Thank you for your support in advance.
Regards,
Ken



  • Hello,

    I am a bit confused by this question - the DAC6311 does not implement open collector digital I/O structures. As with most SPI interfaces the pins are push-pull structures therefore they do not require pull-up resistors. Sometimes pull-up resistors are included to ensure that erroneous data isn't latched by the device when unexpected transients may come out of the host controller's digital pins but this is not a functional requirement.

    If it is a requirement for the host controller, I would suggest consulting that device's datasheet.

  • Hi Kevin,

    Thank you for your feedback!
    I'm sorry that I need to correct my post from Open Collector to Open Drain.

    Here is the circuit schematics from my customer.
    Is it possible to connect with open drain output? If so, I would like to make sure how I chose the pull-up resistor In order to connect with open drain output.




    Thanks,
    Ken

  • Hi Kevin,

    Sorry for rushing you, but it's really appreciated, if you can review their schematics within today.
    Customer is awaiting feedback from us...

    Thank you for your support in advance.
    Regards,
    Ken

  • Hello,

    From the perspective of the DAC6311 there isn't really anything to comment on - the device does not require pull-up resistors to achieve a functional SPI interface, as is typical with SPI interfaces which are often implemented as push-pull structures for both master and slave. I would anticipate the issue is more likely with the FPGA. I don't know anything about the FPGA so I cannot make any comments. I would consult with the FPGA datasheet and makers of the FPGA.

  • I see, Kevin,

    I have asked my customer to make sure the optimized resistor value by themselves, since TI has no information on it.

    Thank,
    Ken