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DAC TLV5630

Other Parts Discussed in Thread: TLV5630

Hello to everyone. I am new with DACs and SPI interface and I am a little confuse about the TLV5630 chip. I can see from the datashhet that the data are captured on clock's falling edge (CPA) but I am not sure about the CPOL. Is the base value of the clock  zero (CPOL=0) or one (CPOL=1).  I would like to drive the chip at 3V with internal Vref and use all the 8 channels so I have to put LDAC low, PRE at 3 volt and vref pin no connected is it right? Finally do I have first to send CTRL0 16 bit and then the 16 bit data for any channel out? I would really apreciate if you could help me to understand the way tha this chip works. Thank you in advance 

  • Hello,

    The best place to observe clock phase and polarity requirements is generally the timing diagrams in the datasheet. Typical setup and hold times for DIN is illustrated with respect to the critical clock edge.

    Per the timing diagram on page 9 the device may idle SCLK high or low. With SCLK idling low (CPOL=0) the falling edge is the critical edge, which would be the second edge so CPOL=1.

    If this is inverted for CPOL=1 the first edge is a falling edge so CPOL becomes 0 but you must be careful to not violate the tsu(FS-CK) specification.
  • Ok so it doesn't matter which polarity I choose if I choose the correct CPHA. The problem that I have is that there is no output although the DIN CLOCK and FS seems to be ok. Thanks a lot for your help!