ADS1281: Discrepancy between test signals and converted data

Gioacchino,


I don't normally cover this device, but I suspect that you are correct that this problem is caused by the anti-aliasing filter. As a test, I would replace the 10kΩ resistors used for R1 and R2 with shorts or something near 100Ω.

For this device the input impedance is rather low (55kΩ). In reality, this is not a constant input impedance, but rather an equivalent impedance created as the input is capacitively sampled and charge is periodically carried away. If there is large series resistance as you have in the anti-aliasing filter, the capacitors sampling the input may not settle correctly and it may appear as a large non-linearity error near 0 input.

I would note that with such large filter resistances, and an ADC low input impedance, you'll already have a very large gain error.

If you're interested, look at the ADS1281 evaluation module users guide and find the schematic. I believe that it uses an OPA1632 as part of the input filtering.


Joseph Wu

Giacchino,


This effect is similar to a "dead zone" behavior which can happen if the op-amp gain in the modulator is low, or if there is leakage in the sampling. In the case of a high series resistance, the charge transfer from input sampling is similar to a leakage.

I focus on the filter resistors because the effect isn't just a simple RC case. The input sampling switches in the sampling capacitor from the ADC in parallel with the filter capacitor.

As an example, you have 100nF on your inputs, when you have a 16pF capacitor (I'm simplifying figure 36 in the ADS1281 datasheet) the voltage seen at the input will momentarily drop as the charge in the 100nF capacitor drops to fill the 16pF capacitor. It should immediately drop 0.016% from the initial value as the charge is redistributed from the full 100nF capacitor to the empty 16pF capacitor. After the input sampling capacitor is switched in, you have one modulator period (1us) to settle the circuit from the input before the filter to make up that small difference. This occurs each modulator period at a 1.048MHz rate.

If you were to reduce the input series resistance and increase the capacitance, then you have a larger input capacitance from which to draw charge. If the input capacitor is 1uF, then the voltage across the sampling capacitor drops 0.0016%, leading to a smaller sampling error. You'll still have the same overall RC time constant, but you'll have less error in the sampling.

Of course this is a simple explanation, and sampling into the modulator is a bit more complicated. The point is that using a larger capacitor will supply more charge into the sampling capacitor so the error will be smaller.

This "dead zone" isn't going to be seen with the oscilloscope. This problem comes from an error sampling the input into the modulator, and is not an external effect.

Out of curiosity, approximately how many codes is your dead zone error, is seems like it might be about 100 codes. Is that correct? How much is that in voltage. I wasn't sure if your y-axis deviation was correct.


Joseph Wu

Gioacchino,


I would look up dead zone with Delta Sigma modulators. There is some reference to this in "Understanding Delta-Sigma Data Converters" by Richard Schreier and Gabor Temes but I'm sure you can find more information on it.

Again, I think the large series input resistance in the filtering causes a similar effect to this, and it should go away with a lower series input impedance.


Joseph Wu