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ADS127L01EVM spi / SSI connection schematic and firmware

Diego Pinzani
Prodigy 70 points
Other Parts Discussed in Thread: ADS127L01, ADS127L01EVM

Hi ,

 I need to integrate the ADC ads127L01 to a tm4c1924 mcu, like as demo board,

and I need to reach the maximum data rate.

Analyzing the demo board schematic the ADC is connected to SSI module number 3 

But I observe that each alternate function pin of SSI3 are shorted together,

see in the demo board schematics   for example (SSI_clk) PQ0 is together PF3,

I don't know why.

Since I'm drawing a new schematic I have some dubt: how connect the SPI and in whitch manner the ADC is readed by MCU.

Then my question is if is possible receive the firmware source code (or part of it) of demoboard ADS127L01EVM in order to understand

the interfacing to the MCU and the firmware technique to obtain maximum data rate.

I'm planning use SPI and uDMA to do it.

Best Regards

Diego

 

  • 0
    TI__Guru 57336 points
    Hi Diego,

    Thanks for your interest in the ADS127L01!

    The sharing of various ports on the Tiva MCU was simply a way to give us the flexibility to re-use this MCU design in future EVM development. It is not a requirement for use the ADS127L01.

    We do not have approval to share the source code for the EVM firmware. However, if you have any specific questions about using the ADS127L01 interface, please do not hesitate to ask us. I can tell you that we had to use the uDMA in order to collect data at the maximum data rate.

    Best Regards,
  • 0 in reply to Ryan Andrews
    Prodigy 70 points

    Dear Rayan

    thank for your support

    I'm planning to use an gpio connected to ADC DRDY  as trigger for uDMA that send 2 words (total 32 bit ) to SPI.

    Another uDMA channel retrive data from SSIRX fifo and move the 32 bit sample  in a PING PONG buffer mapped in ram

    this can be do only each 2 samples because an SSI RX uDMA burst transfer request is asserted whenever the amount of data in the receive FIFO is 4

    when the Ping buffer is full filled I send it out from ethernet port, while the other PONG buffer continue to collect data.

    At the moment I'm writing the source code to setup various uDMA channels, and I'm studing the datasheet to do it. 

    I' planning to test the code connecting a signal generator to GPIO as DRDY, shorting the SSI TX and RX and trasmitting to SSI TX an incremental value.

    i will expect a Sawtooth.

    I hope this approch will be correct in order to collect maximum SPS.

    Many thanks,  Best Regards

    Diego