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ADS7953: ADS7953 Intermittent SPI Clock

GregGable
Expert 3610 points
Part Number: ADS7953

The SPI clock in my application is not continuous after assertion of CS.  Is that okay or does the SPI clock need to immediately clock out all output bits?

Thanks,

Greg

  • 0
    TI__Expert 3675 points

    Hi Greg,

    You can read data with an intermittent SCLK.
    As long as you operate within the min and max timing specs, the SCLK can be intermittent.

  • 0 in reply to RahulVK
    TI__Expert 3610 points
    Thanks Rahul.

    So, is the SAR conversion occurring when the SPI clock is stopped? Is there any timing constraint for how long I can take to complete the 16 SCLK’s needed to complete the conversion/data?

    Thanks,
    Greg
  • 0 in reply to GregGable
    TI__Expert 3675 points
    Hi Greg,

    In this device, the device outputs data when the conversion is in progress. Hence SCLK is the conversion clock.
    There is a max spec of 20-MHz on SCLK and there is no min spec.

    Halting the conversion clock mid-way is as good as running the ADC conversion at the highest SCLK period in the frame. You may want to check on reference stability, if the conversion clock is going to be halted for a while. This is because the conversion result can be way off the reference changes during an on-going conversion.

    Please note that all device specifications in the data-sheet are with continuous SCLKs. You could a run a sanity check by intentionally delaying each of the SCLKs by the maximum period you estimate.

    Could you please share how long do you estimate would be the "no-SCLK" period during an on-going conversion? Would this period occur at any time in a frame. I am asking this because LSB decisions are much more sensitive to reference stability than MSB ones (relatively speaking).