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ADS7955: The SPI timing questions(td2 and td3)

Part Number: ADS7955

Hi Team,

  Could you help check below questions about the td2 of ADS7955 SPI?

  My customer got td2=33.2ns on their board which was much higher than the MAX of td2(17ns) for 5V power supply,the SCLK=1MHz and SDO connected with 50pf load.

  They also got td3=14.75ns which was higher than the MAX value in datasheet.

  Could you help check the test condition of td2 and td3 in ADS7955 datasheet? What's the clock frequency and test on which point(near master or slave)?

  Is there any risk if these two timing can't satisfy the datasheet? And what's the solution?

Best Regards,

Nick Dai

  • Hi Team,

     There are more questions from the customer.

     The schematic is shown in below.The customer test td2 and td3 at the SDO and SCLK pin of ADS7955,and they have replace R and C in schematic with 50pf capacitor load.

    They got below figure for td2 test.

    Questions:

    1.What's the VOH and VOL for td2 and td3 test? Could the cusomer use the value mentioned in datasheet(VOH=VDD-0.2,VOL=0.4)?

    2.Did the customer test on correct test point for td2 and td3?

    3.Will the td2 and td3 value change if the customer use low rate SCLK(1MHz)?

    4.Will we check td2 and td3 in our ATE?

    The customer wants to understand is there risk in their design,please help to check these questions,thank you.

    Best Regards,

    Nick Dai 

  • Hi Nick

    Please see my answers below

    1.VOH and VOL levels for timing specs are as per datasheet (VOH= VDD-0.2 , VOL= 0.4V)

    2. Yes these parameters should be measured on device side

    3. Timing delays mentioned in datasheet should remain the same irrespective of clock freqency.

    4. I need to check for delay measurement on ATE. I will get back to you on this

    The delay mismatch could be because of parasitic trace capacitance and trace impedance. I would suggest to disconnect R1019 (1K) on SDO line and do timing measurements.

    Also what is the trace length between device digital pins and host controller.

    Thanks & Regards

    Abhijeet Godbole

  • Hi Abhijeet,

       Thanks for your feedback.

       The customer tested td2 and td3 at the SCLK and SDO pin of ADS7955 with only 50pf load,and they got below two scopes.

       In datasheet,we define td2 as SCLK falling to SDO next data bit valid and td3 as 16th SCLK falling edge to SDO 3-state.

       How to understand the SCLK falling? Could I understand as the voltage reach to VIL(0.8V when +5V power supply)?

       However,I my understand is correct,then the td2 and td3 will be a minus value.

       Could you help check what's the td2 and td3 in below two figures?(Yellow:SCLK,Blue:SDO). 

       

    Best Regards,

    Nick Dai

  • Hi Nick

    While defining datahseet timing delays (SCLK  falling to SDO 3- state / SCLK falling to SDO next data valid)  measurement is not exactly triggered at VOH/VOL. for most of the parts  we typically do it from 50% to 50%. If you measure from 50% of SCLK falling to 50% of SDO then your reading should be valid

    I can see that SCLK falling edge takes to long get to GND and looks to be additional cap load on that pin. Can you please check what is the cap load value. One thing you can try is to reduce 100 Ohm series resistor value to 10 Ohms and see if that improves the response.

    Thanks & Regards

    Abhijeet

  • Hi Abhijeet,

      Thanks for your support.

      One more question,what's Vdd mean in logic level VOH spec? And the high level voltage of SDO in customer board is 4.6V when the device is in +5V power supply,whey there is 0.4V drop in SDO logic high output?

    Best Regards,

    Nick Dai

  • Hi Nick

    Vdd is referred to digital supply of device. if customer is seeing 4.6V on SDO during logic high it could be due to fairly high drive current requirement on this pin.

    1) Can you ask customer to probe digital supply pin of ADS7955 and SDO together. Is there a series resistance in digital supply and device VBD pin.

    2) As of now do they have 1k populated on SDO line? Also Can customer remove 2.49k termination resistor on SDO line and see the performance

    Thanks & Regards

    Abhijeet