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ADS8363: ADS8363 Interface, clock pulses

Bob Rowland
Prodigy 180 points
Part Number: ADS8363

I am using the ADS8363 with an STM32F407 processor and interfacing to the ADS8363 with the processor’s SPI interface. I have not figured out a way to send twenty clock pulses to the ADS8363, instead I am sending three eight bit bytes to the ADS8363 immediately after pulsing the Convst/Rd high. When I pulse the Convst/Rd high the ADS8363 Busy goes high and stays high for eighteen clock pulses, but the SDOA line always low. Could the problem be related to sending 24 clocks instead of 20 clocks between pulsing the Convst/Rd? Or is something else wrong. I am using the ADS72/8363 eval board. Here is the setup.

 J2 is open, M0 and M1 are both high, should be in Mode 4

J5 jumper connects Convst to Rd.

CS is tied low.

Clock = 1.78MHz

No configuration is sent to the ADS8363

Convt/Rd is pulsed with a high pulse 500nS wide followed by 24 clock pulses.

Convt/Rd rise to first clock rise = 920nS

  • 0
    Prodigy 180 points

    After spending a lot of time checking signals I came to the conclusion I had somehow damage this ADS8363 so I purchased another eval board. This time I never connected the SDOA output to the processor. But the results are exactly the same with the new board, SDOA is always low.   The only changes I made to the boards set up was J6 and J2. J6 jumper is connected to 3.3V. J2 jumper was removed to put it into Mode 4, however I have also tried it with J2 connecting M0 to ground, SDOA and SDOB are always low. CS is tied to ground.

     The amplitude of all of the input signals is about 2.9V to 3.0V which is well within spec for AVDD = 3.3V. Both supplies and grounds look good, very little noise. I tried reducing the Convst/Rd pulse to 320nS which had no effect. I also found that when I tried to write to either DAC the ref doesn’t change, they are both always 2.5V. The only thing that seems to be working is Busy, Busy goes high and stays high for eighteen clock pulses. SDOA appears to be tri-stated because there are 100mV pulses on SDOA that correspond to the clock. The program sequence is: it waits for Busy to be low then Convst/Rd is pulsed high followed by 24 clock pulses, then a 2.5uS delay, Convst/Rd is pulsed again followed by 24 more clock pulses. I am really baffled by why it’s not work, but I am sure I must be doing something wrong now that I have two eval boards working exactly the same.

     

  • 0 in reply to Bob Rowland
    TI__Intellectual 1205 points
    We are looking into your question. From what you describe, I do not see an issue with your setup. Can you capture the digital waveforms and attach them to your post? It seems like there is a clue that we are missing.
  • 0 in reply to Bryan McKay
    Prodigy 180 points

    Here is a screen shot of the signals going and coming from the ADS8363.  In this test I should be continuously converting and reading in Mode IV.  There were no jumpers on J2, both M0 and M1 are high.  Both inputs are +1.0V.  Both REFio are 1.5V   I have also tried it with a jumper shorting M0 to ground, no change.  CS is tied to ground.  It is not clear to me if bit 12 of the config register (R0) should be set high or low.  In the screen shot it is set high, but I have tried it set to 0.  Made no difference.  I would be easily convinced that the ADS8363 is bad, but now I have two eval boards doing the same thing.  So it must be something I am doing wrong.

    Thanks for your help.

    Bob

  • 0 in reply to Bob Rowland
    Prodigy 180 points

    I copied the image of the Logic Analyzer and added it to the bottom of my post in Richfield format, but it doesn’t look like image is attached to my last post. I am not sure how to insert or attach an image from a pdf.

  • 0 in reply to Bob Rowland
    Prodigy 180 points
    I just attached a PDF. Thank you for your help!
  • 0 in reply to Bob Rowland
    TI__Intellectual 1205 points
    We have been looking at your waveforms.

    One thing we noticed is that SDI is changing on the falling edge of SClk. The signal actually gets coupled into the ADC on the falling edge, so it should be driven on the rising edge. Changing it on the falling edge could result in wrong or indeterminate data being coupled in. However, you mentioned that you are setting Bit12 high, but have tried setting it low, and it made no difference; so that cannot be the whole problem. In any case, to make writing to the registers more reliable, you should drive data on the rising edge of SClk. (This may explain why programming the DAC's was not successful, but you should still see data on SDO.)

    Your waveform diagram shows a label "D0 Freq: 960Hz" at the bottom, which corresponds to CONVST. This would be below the specified minimum sample rate for this ADC. However, the time scale at the top would seem to indicate that you are asserting a CONVST every 16us or so, which is about 60kHz in 20-clock mode or 30kHz in 40-clock mode. In either case, that would be OK. So if the label at the bottom is correct, then you need to speed up your cycle; but if the time scale is correct, then your signals are just fine for frequency. I would think that even below the minimum sample rate, the ADC should still output data, even if it does not meet performance specs.

    Your waveform graphic shows two cycles of 24 SClks. BUSY goes high for the first one, then stays low for the second one. Does BUSY go high again for the third cycle?

    One last question for now: Where are you probing to collect waveforms? Is it possible that the SDOA line is not connected to your controller?
  • 0 in reply to Bryan McKay
    Prodigy 180 points

    Hi Bryan,

     

    Thanks for the response.

     I initially thought SDI should be changing on the rising edge and that was how it was initially, but at some point I thought it was wrong and changed it to the falling edge. I switched it back to the rising edge.

     I believe what is going on with D0 (Convst/Rd) frequency is between reads I am printing the data which puts a large delay between reads. The logic analyzer is calculating the frequency of DO including that delay. The scale above is correct, but hard to read. The actual timing is:

    Clock Freq.                                          -              1.78MHz

    Convst/Rd Pulse width                  -              310nS

    Convst/Rd rise to Clock rise         -              880nS

    All Signal Amp.                                  -              2.9V -3.0V          

     I can’t program the processor to send 20 SPI clocks, so instead I am sending 24 bits (three eight bit bytes) and not using the last four bits. I always send two packets. Each pack starts by pulsing the Convst/Rd high followed by 24 clock cycles. Before I pulse the Convst/Rd I check the Busy to make sure its low. Immediately after the Convst/Rd pulse I check the Busy again to make sure I am syced with the ADS8363.

     

    I attached to more Logic Analyzer captures, the first is a single read with two 24 bit packets, the second is zoomed out showing multiple reads. In both the SDI is now changing on the rising edge.

     

    The third attached capture is a single write to DAC1 with a value of 2730 (0xAAA or 0x1010101010101010). This write didn’t change the DAC value, its still about 2.4V

     I am using an ADS8363 eval board and monitoring SDOA on pin 13 on J3. I did have it connected to the processor, but I thought maybe the processor was pulling it down, so now it is not connected to anything. I have verified it is not shorted to ground and checked it using both the scope and logic analyzer. I even checked pin 25 on the ADS8363, it’s always low.

     It seems to me since SDOA never changes, is always low, and the writes don’t seem to affect the DACs that I must have a basic problem of some type, It is very strange that the Busy is correct which seems to indicate the Convst/Rd and the clocks are correct, but there is no output.

     It is still not clear to me if R0 (Bit 12) should be set high or low during a read. The description says high updates the config register, but during a read I am not updating the config register? I have tried with R0 = 0 and R0 = 1, didn’t make any difference, SDOA is still always low.

     I have been working in electronics for fifty years and this is one of my more baffling problems.

     Thanks again for your help.

     Bob

  • 0 in reply to Bob Rowland
    TI__Guru**** 168445 points

    Hi Bob,

    The reason you are not getting any data out on the SDO lines is because there is no clock under your Convt/Rd pulse.  The actual start of conversion is not dependent on any clock edge, which is why you see BUSY go high.  The read function however, is only qualified by a falling clock edge (see tS1 and tH1 in section 7.9).  Getting a synchronous RD+CONVST with a true SPI interface such as you have here can be accomplished by 'writing' to the RD+CONVST as described in this application note (see section 3.2.2):

  • 0 in reply to Tom Hendrick
    TI__Intellectual 1205 points
    Bob:
    Tom is correct. I have verified this in the lab. When I apply the same conditions as you have, I get no data out. And, like your condition, BUSY goes ahead and says that a conversion is being done. But when the SClk is running while I assert the CONVST/RD pulse, then everything works.

    Tom:
    Thank you! You are exactly right.
  • 0 in reply to Bob Rowland
    Prodigy 180 points

    You were right, now I am getting data back on SDOA. 

    Thank you both so much, I really appreciate the help.

    Bob