ADS1198: False leadoff detection for negative channels in AD1198 continuesly, Critical issue

Bhairu Patil1

Part Number: ADS1198

Dear All,

I am facing a issue with ADS198 False leadoff detection, The device is detecting a lead off for negative channels even when the all leads are connected to electrodes or simulator, The LOFF_STAT_N is changing continuously. Please provide your inputs to fix this issue at the earliest.

The following are the wrong values read from ADS1198 for negative channels.

Address	Register	Values read from AD1198	Description
13h	LOFF_STATN	0x0D, 0x1D, 0xDF, 0x1F, 0x9F	The Values are changing continuesly, even when all the leads are conneccted to Electrodes or simulator. This is a serious issue.

The settings for the register for Lead-0ff detection is as per following.

Address	Register	Value set	Description
04h	LOFF	0xE3	Lead-off comparator threshold: positive side 70%, Negative side 30% Lead-off detection mode: Current source mode lead-off Lead-off current magnitude: 4 nA Lead-off frequency: DC lead-off detection turned on
17h	CONFIG4	0x02	Continuous conversion mode, Lead-off comparators enabled
0fh	LOFF_SENSP	0xFF	All Positive channels are selected for lead offf detection
10h	LOFF_SENSN	0xFF	All Negative channels are selected for lead offf detection

Please, go through the following schematics. and provide me your inputs.

Regards,

Bhairu

over 7 years ago

0 Brian Pisani over 7 years ago

TI__Mastermind 38745 points

Hello Bhairu,

It looks from your schematic that the negative inputs are all connected to the WCT output. Is this true? The image is a little pixellated.

If that is the case, those inputs cannot become "disconnected" so the comparator is probably triggering when the voltage at the pins drops beneath 30% of AVDD.

In any case, you should disable lead-off detection for any input pins that are directly connected to the WCT amplifier since that would provide no useful information.

Brian

0 Bhairu Patil1 over 7 years ago in reply to Brian Pisani

Intellectual 570 points

Dear Brian,

The details of ADS1198 input channels is as per below.

ADS1198 i/p Channels	Leads Connected
IN1P	V6
IN2P	LA
IN3P	LL
IN4P	V2
IN5P	V3
IN6P	V4
IN7P	V5
IN8P	V1

IN1N	WCT
IN2N	RA
IN3N	RA
IN4N	WCT
IN5N
IN6N
IN7N
IN8N

Below is the the ADS1198 schematic

BW_AD1198.pdf

Regards,

Bhairu

0 Bhairu Patil1 over 7 years ago in reply to Bhairu Patil1

Intellectual 570 points

Dear Brian,

The RA lead is connected to IN2N & IN3N(Negative inputs of channel 2 & 3 ). Please, provide your inputs on what could be the cause for this issue.

Regards,

Bhairu

0 Brian Pisani over 7 years ago in reply to Bhairu Patil1

TI__Mastermind 38745 points

Hey Bhairu,

Is the RL electrode connected to the simulator/patient when this is occurring? If not, the inputs are "floating" which could cause strange behavior in the lead-off detection.

If it is connected, perhaps try decreasing the detection threshold using the COMP_TH[2:0] bits in the LOFF register.

Brian Pisani

0 Bhairu Patil1 over 7 years ago in reply to Brian Pisani

Intellectual 570 points

Dear Brian,

The following are the details for the questions you asked.

Is the RL electrode connected to the simulator/patient when this is occurring? -

We have seen this issue only when RL electrode is connected to the patient. I will try by decreasing the detection threshold as you suggested.

Today, I have analyzed the negative channels lead off status LOFF_STATN, and it is tabulated as follows.

	The LOFF status for Negative channels(LOFF_STATN)
	Negative Channels LOFF status
	WCT	WCT	WCT	WCT	WCT	RA	RA	WCT
LOFF_STATN Value read	IN8N_OFF	IN7N_OFF	IN6N_OFF	IN5N_OFF	IN4N_OFF	IN3N_OFF	IN2N_OFF	IN1N_OFF
0x0D	0	0	0	0	1	1	0	1
0x1D	0	0	0	1	1	1	0	1
0xDF	1	1	0	1	1	1	1	1
0x1F	0	0	0	1	1	1	1	1
0x9F	1	0	0	1	1	1	1	1
0xFF	1	1	1	1	1	1	1	1
0x0F	0	0	0	0	1	1	1	1
0x08	0	0	0	0	1	0	0	0

If you see in 1st and 2nd row, IN3N comparator has detected lead off, whereas IN2N comparator has not detected lead off, even if inputs for both comparators are connected to RA lead. I am wondering how this could happen, and I am not getting about why the both comparators are showing the 2 different results with same inputs?. Please provide your inputs on this ASAP.

The above issue has seen after 12 hours patient wearing the device. Soon after restarting the device also issue was still observed.

Thanks and Regards,

Bhairu

0 Brian Pisani over 7 years ago in reply to Bhairu Patil1

TI__Mastermind 38745 points

Hey Bhairu,

The comparator threshold accuracy is listed as +/-30 mV on page 4 in the datasheet so it's possible that the thresholds between channels is slightly different. One way to make this more work better besides decreasing the threshold voltage would be to increase the lead-off current. The current 4 nA is really really small. There are plenty of leakage paths which could be causing non-idealities that could affect the circuit's functionality. A larger current would have less of a percentage of it's nominal voltage leak through non-ideal behavior.

Brian

0 Bhairu Patil1 over 7 years ago in reply to Brian Pisani

Intellectual 570 points

Dear Brian,

As you suggested the Lead off comparator threshold changed from 70%(+ve channel) ,30 %(-ve channel) to 95%(+ve channel) , 05 %(-ve channel) by setting the COMP_TH[2:0]:= 000( i.e. LOFF(0x04) = 0x03), with these settings lead off has been detected for all positive and negative channels except for RLD. Tomorrow I will try by increasing lead off current also if required..

I have gone through the datasheet, and done the following things in order to enable RLD LOFF detection.

RLD_LOFF_SENS is enabled. by setting CONFIG3(03H) = 0xCE.

With these change whenever there is a Lead off , it shows a lead off for all the positive channel & CH2 & CH3 of negative channel (CH2N & CH3N). I wanted to read the status of RLD_STAT bit of CONFIG3 register to ensure the RLD lead off state.

I am using read data continuous command for data retrieval upon Data ready interrupt. Please provide more details to read the CONFIG3 register value after each data retrieval for every sample. Please share a sample code to detect RLD lead off.

Please, clarify the following.

Necessity of The RLD drive internal amp to be powered down for RLD detection & if required how to powered down RLD drive internal amp.
Which lead off detection mode will be preferred. Current source mode lead-off (default) or Pull-up/pull-down resistor mode lead-off.
Which method is more suitable between AC leadoff 7 DC leadoff.

Thanks and Regards,

Bhairu

0 Brian Pisani over 7 years ago in reply to Bhairu Patil1

TI__Mastermind 38745 points

Hello Bhairu,

You are correct in noting that the RLD lead-off functionality cannot be used during normal operation as is noted on page 57 in the datasheet. To determine the lead-off status of the RL electrode, you will have to power down the RLD by clearing the PD_RLD bit in the CONFIG3 register and then read back the CONFIG3 register using a RREG command.

We do not have any code which shows this, but perhaps you could develop a system where if multiple leads are detected off on the patient, you also check the status of RL using the steps I described above.

DC lead-off is the better of the two detection methods because it provides a detection indicator. AC lead-off requires that you develop your own algorithm for determining lead-off from the data you collect from the device.

Brian

0 Bhairu Patil1 over 7 years ago in reply to Brian Pisani

Intellectual 570 points

Dear Brian,

Thank you for your quick reply and clearing my doubt. I have gone through an example procedure to turn on dc lead-off given in the Lead-Off subsection of the Quick-Start Guide section, where dc excitation signal is chosen as an pull-up/pull-down resistor. I understand that current source/sink gives larger input impedance compared to the 10MΩ pull-up/pull-down resistor.

Please, clarify the following.

Which DC excitation is prefered, among current source/sink or 10MΩ pull-up/pull-down resistor.
Is there are any implications on ECG signal by increasing magnitude of current for the current lead-off mode?.

Thanks and regards,

Bhairu

0 Brian Pisani over 7 years ago in reply to Bhairu Patil1

TI__Mastermind 38745 points

Bhairu,

The current sources are more preferred because the input impedance is larger.

The only thing that would change is there would be a dc offset introduced by the current multiplied by the resistors on the front end, but that will not be more than a couple of millivolts. Offset is not uncommon in ECG applications anyway.

Brian

0 Bhairu Patil1 over 7 years ago in reply to Brian Pisani

Intellectual 570 points

Dear Brian,

Thank you for your inputs,

I have done the following changes to detect RLD lead off

1) RLD sense is enabled.

2) Lead off Current is set to 16nA.

3) Current sense mode Lead off is selected.

i.e CONFIG3 reg(03H) = 0xCE

LOFF reg(04H) = 0x0F

During Runtime, For every 1 second read the status of RLD_STAT of config3 by following procedure.

Stop_Read_Data_Continuous
PD_RLD bit of Config3 register is set to LOW (CONFIG3 reg(03H) = 0xCA),
read the RLD_STAT of config3.
PD_RLD bit of Config3 register is set to High (CONFIG3 reg(03H) = 0xCE),
Start_Read_Data_Continuous;

With these following results for RLD lead off detection are observed when RLD lead is disconnected from the body.

RLD Lead OFF is detected correctly via RLD_STAT of config3 when it is connected to simulator.
No lead off detected When device is worned onhuman body.

When we found the root cause we found that, whenever body skin or hand touches to the Connector shield/ Device casing which is connected to AVSS & DGND of ADS1198 it is not detecting lead-off, and ECG is propper even though RLD is not connected.

I have gone through the datasheet, but didn't get any solution to fix this issue. please clarify the following

how the human body getting propper biasing without RLD lead connected just by touching skin to Connector shield/ Device casing which is connected to AVSS.
how the RLD and AVSS are related.
HOW to detect RLD lead- off for above mentioned issue
No RLD leadoff detection upon touching skin to Connector shield/ Device casing which is connected to AVSS.

Thanks and Regards,

Bhairu

0 Bhairu Patil1 over 7 years ago in reply to Brian Pisani

Intellectual 570 points

Dear Brian,

Thanks for your inputs.

I have read the RLD leadoff status correctly by using RLD_STAT bit whenever there is a lead-off with simulator. but I have not detected RLD lead_off whenver device is worned on human body.

The root cause for this is human skin is touching to the Connector shield/ device casing(device body) which is connected to the AVSS & DGND of ADS1198.

Please clarify the following.

How RLD , AVSS & DGND are related.
How the human body getting propper bias whenever human skin is touching to the Connector shield/ device casing even though RLD lead is disconnected from the human body ( ECG is propper).
Please suggest to fix the above issue.

Thanks and Regards,

Bhairu

0 Brian Pisani over 7 years ago in reply to Bhairu Patil1

TI__Mastermind 38745 points

Hello Bhairu,

I believe I know what is going on here. If the patient touches ground, you can assume all of the ADC inputs will have a voltage of 0V. The PGAs, however, have an output limit of 200 mV above AVSS. So let's say that the output voltages of the PGAs are then 200 mV.

Now refer to Figure 50 in the datasheet. The RLD amplifier is disabled so you can assume the output of the amplifier is high impedance. The output is also disconnected from the patient so the only place current flows is through the 16 nA lead-off current source to AVSS.

Assuming some of those RLDxP/N switches are closed, the RLDINV pin will also have a voltage of 200 mV. The 16 nA lead-off current flows through R5 in your schematic. The voltage at RLDOUT, which is where the comparator observes the voltage, is 200 mV - (16 nA * R5) = 185 mV.

You have the COMP_TH[2:0] bits set to 5% so the comparator will only trigger when the voltage at RLDOUT is below 0.05 * 3 V = 150 mV. Since the voltage is 185 mV, it will not trigger.

By the way, there is also a voltage drop accross the 220 kOhm resistors but it is small compared to that of R5 so I ignored it.

To fix this, I suppose you have 2 options.

Clear all RLDxP/N bits so the current will have nowhere to travel and the voltage at RLDOUT will always go low no matter what.
Move the comparator threshold to at leas 7.5%. This will allow the comparator to trigger at 225 mV.

Regards,

Brian Pisani

0 Bhairu Patil1 over 7 years ago in reply to Bhairu Patil1

Intellectual 570 points

Dear Brian,

Thanks for your inputs, I have tested both the options as you suggested to detect RLD lead_off by reading the RLD_STAT bit .

option 1. Clear all RLDxP/N bits so the current will have nowhere to travel and the voltage at RLDOUT will always go low no matter what.

RLD_STAT bit is always read as '0'.

option 2. Move the comparator threshold to at leas 7.5%. This will allow the comparator to trigger at 225 mV.

Tested with comparator threshold 7.5% and the results are as follows.

- RLD_STAT bit is read as '0' if patient touches the system ground.

- RLD_STAT bit is read as '1', as expected if patient has not touching the ground.

if comparator threshold is set to 10%, the RA false leadoff is getting detected.

The voltage is measured a/c RLDIN/RLDOUT and the results are as below.

case	Voltage a/c RLDIN/RLDOUT in Volts
All leads are connected to body	1.482
only RL lead is disconnected	0
only RL lead is disconnected & patient touches system gnd	2.96

I am more interested in detecting RLD leadoff, whenever patient is touching the system ground, because in our case mechanical casing of the device is connected to ground, which touches the patients body always.

Please, clarify the following.

why voltage across the RLDIN/RLDOUT is changing to 2.96V from 0V, whenever GND is touching to the patients body?.

Please reply at the earliest.

Thanks and Regards,

Bhairu

0 Brian Pisani over 7 years ago in reply to Bhairu Patil1

TI__Mastermind 38745 points

Bhairu,

Can you please clarify under which circumstances you see these results:

Bhairu Patil1 said:

The voltage is measured a/c RLDIN/RLDOUT and the results are as below.

case Voltage a/c RLDIN/RLDOUT
in Volts

All leads are connected to body 1.482

only RL lead is disconnected 0

only RL lead is disconnected &
patient touches system gnd 2.96

Do they correspond to when RLDP/N bits are set or cleared? Is the RLD amplifier powered down? The only reason I could think that RLDOUT would go to 2.96 is when the RLD amplifier is powered on with some RLDP/N bits set. In that scenario, the inverting gain would produce a voltage near AVDD when the inputs are equal to ground.

When you tested option 1, were you able to probe the output of the RLD amplifier with an oscilloscope to see the voltage at that node? It seems strange to me that with a pull-down current source and absolutely nothing connected to the node that the voltage would remain constant.

By the way, in case you need a reference for how this circuit works for your tests, you can think of it as a combination of Figures 49 and 50 in the datasheet.

Brian

0 Bhairu Patil1 over 7 years ago in reply to Brian Pisani

Intellectual 570 points

Dear Brian,

Thank you, for your inputs.

Clarification : The results shared in previous post are under following circumstances.

Config3 register set to 0xCE ; // RLD_LOFF_SENS enabled
LOFF register is set to 0x0F ; // comparator threshold 95 - 05 % , 16na leadoff current . Current source mode, DC leadoff detection
RLD_SENSP register set to 0x02 ; // channel 2 positive(LA)
RLD_SENSN register set to 0x02 ; // channel 2 negative(RA)

The voltage is measured a/c RLDIN/RLDOUT during above condition and the results are as below.

case	Voltage a/c RLDIN/RLDOUT in Volts	Lead off detecction
All leads are connected to body	1.482	No
only RL lead is disconnected	0	Yes
only RL lead is disconnected & patient touches system gnd	2.96	NO

Option 1: The RLD_STAT is read to detect RLD_leadoff under the following circumstances and the results are as below.

Config3 register set to 0xCE ; // RLD_LOFF_SENS enabled
LOFF register is set to 0x0F ; // comparator threshold 95 - 05 % , 16na leadoff current . Current source mode, DC leadoff detection
RLD_SENSP register set to 0x00 ;
RLD_SENSN register set to 0x00 ;

case	Voltage a/c RLDIN/RLDOUT in Volts	Lead off detecction
All leads are connected to body	1.482	NA
only RL lead is disconnected	1.482	NO
only RL lead is disconnected & patient touches system gnd	1.482	NO

To read RLD_STAT bit of Config3 register the following procedure is followed, The overall time it is taking 360us,

send SDATAC command //Stop_Read_Data_Continuous
write 0xCA into config3 register. // RLD_buffer powered down
write0xCE into config3 register. // RLD buffer is enabled
read RLD_STAT bit of Config3 register
send RDATAC command //Start_Read_Data_Continuous

Please clarify the following ASAP.

Why Voltage a/c RLDIN/RLDOUT pin is constant in all the cases in option1? & why RLD_STAT bit is read as 0 for 'RLD leadoff condition in option1.
how much duration is required to get the stable ECG data from ADS1198 after reading RLD_STAT bit?.
How to read the RLD leadoff status properly, when there is leadoff & patient touches the system ground?.

Thanks and Regards,

Bhairu

The voltage is measured a/c RLDIN/RLDOUT and the results are as below.

case	Voltage a/c RLDIN/RLDOUT in Volts
All leads are connected to body	1.482
only RL lead is disconnected	0
only RL lead is disconnected & patient touches system gnd	2.96

0 Brian Pisani over 7 years ago in reply to Bhairu Patil1

TI__Mastermind 38745 points

Hello Bhairu,

It looks like in all the cases you try to detect RLD lead-off, the RLD amplifier is powered on. Recall that the RLD lead-off will not function properly when the RLD amplifier is powered on (see page 57 of the datasheet).

In your sequence, it looks like you are disabling the RLD amplifier, then immediately re-enabling it, then reading the status of the RLD_STAT bit. Is this the case? This will not work because the RLD amplifier would be on when you read the lead-off status.

In addition, you will probably have to wait some time after the RLD amplifier is turned off before the voltage is low enough to trigger the lead-off comparator since there will be some capacitance in the circuit and the electrodes. For example, if the circuit has even 2 pF of parasitic capacitance at the output of RLD, it will take 170 us for the 16 nA current source to bring the voltage on the net low enough to trigger the comparator.

It will read zero because the RLD amplifier is on.
Are you referring to time it takes the RLD amplifier to turn on after it has been enabled? I do not believe we have any data on this.
Refer to my above comments.

The ADS1198 RLD lead-off circuit does not lend itself well to continuous lead-off detection. My recommendation is to only check RL lead-off under certain circumstances. For example, if multiple other electrodes indicate lead-off or if your R detection function fails to detect a proper ECG waveform.

Regards,

Brian Pisani

0 Bhairu Patil1 over 7 years ago in reply to Brian Pisani

Intellectual 570 points

Dear Brian,

Thank you for your inputs.

The RLD detection issue when RLD lead is disconnected and the patient touches system GND,

-- This issue is fixed in our device by isolating patient body being connected to system GND.

The following configuration is set to detect RLD.

Config3 register set to 0xCE ; // RLD_LOFF_SENS enabled
LOFF register is set to 0x0F ; // comparator threshold 95 - 05 % , 16na leadoff current . Current source mode, DC leadoff detection
RLD_SENSP register set to 0x02 ; // channel 2 positive(LA)
RLD_SENSN register set to 0x02 ; // channel 2 negative(RA)
RLD_STAT from config3 register is read correctly for every 1 sec, if there is RLD lead- off.

Please, provide the clarification on the following ASAP.

Is it fine to read RLD_STAT bit of config3 register for every 1 Second?.

Thanks and Regards,

Bhairu

0 Brian Pisani over 7 years ago in reply to Bhairu Patil1

TI__Mastermind 38745 points

Hello Bhairu,

The issue is not the frequency of the reads, it is more related to the robustness of the lead-off circuit. The reason I recommended only reading under certain circumstances is because to get an accurate lead-off detection, you must turn the RLD amplifier off, wait some time, and then read the bit. This is not ideal to have to do constantly since it requires powering down the RLD amplifier. During normal operation, you do not want to have to power down RLD since it could affect your ECG measurements.

Brian

0 Bhairu Patil1 over 7 years ago in reply to Brian Pisani

Intellectual 570 points

Dear Brian,

Thank you, very much for your inputs and continues support. As per your suggestion, We are not reading status of the RLD_STAT bit.

We have consider the following changes as you suggested to fix the false lead off detection.

Config3 register set to 0xCC ;
LOFF register is set to 0x0F ; // comparator threshold 95 - 05 % , 16na leadoff current . Current source mode, DC leadoff detection
RLD_SENSP register set to 0x02 ; // channel 2 positive(LA)
RLD_SENSN register set to 0x02 ; // channel 2 negative(RA)

With these changes the following results we observed.

Leads Disconnection from patient body	ADS Channel	LOFF_STATP	LOFF_STATN	Lead-off detection
All leads	--	0xFF	0x06
RL	--	0xFF	0x00
RA	IN2N/IN3N	0x00	0x06	RA
V6	IN1P	0x01	0x00	V6
LA	IN2P	0x02	0x00	LA
LL	IN3P	0X04	0x00	LL
V2	IN4P	0X08	0x00	V2
V3	IN5P	0X10	0x00	V3
V4	IN6P	0X20	0x00	V4
V5	IN7P	0X40	0x00	V5
V1	IN8P	0X80	0x00	V1

If we seen the above table, Whenever only RL lead is disconnected from the patients body, we are receiving LOFF_STATP as 0xFF from ADS1198.

For RL leadoff detection we are following the below method.

whenever LOFF_STATP is read as 0xFF , we are interpreting that RL is disconnected. and we are not processing the ECG signal.

Please, Clarify on the following ASAP.

Is above method for interpreting RLD lead detection is valid?.
Is there any suggestion for improving RLD lead-off detection?.

Regards,

Bhairu

0 Brian Pisani over 7 years ago in reply to Bhairu Patil1

TI__Mastermind 38745 points

Hello Bhairu,

1. That should work most of the time.
2. In this scenario, it's possible that if only RL comes off, that the current sink attached to RA could sink one of the sources on one of the positive inputs and the voltage at that positive input could remain low enough that the comparator does not trigger. In that scenario, you would read the all the LOFFP bits but one set. One way to improve it would be to check for all scenarios where at least 7 of the 8 LOFFP bits are set. The following shows the logic:

(LOFFP == 0xFF) ||
(LOFFP == 0xFE) ||
(LOFFP == 0xFD) ||
(LOFFP == 0xFB) ||
(LOFFP == 0xF7) ||
(LOFFP == 0xEF) ||
(LOFFP == 0xDF) ||
(LOFFP == 0xBF) ||
(LOFFP == 0x7F)

Regards,
Brian

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ADS1198: False leadoff detection for negative channels in AD1198 continuesly, Critical issue