• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 640 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1194: DRDY is LOW in RDATAC mode

Arash_
Prodigy 230 points
Part Number: ADS1194

I have programmed the chip to RDATAC mode, but DRDY signal is not as datasheet which is normaly high and goes low for 1.96us when it has data ready. My DRDY is normaly low and goes high for 1.96us at the sampling rate frequency. Is this a problem of datasheet or my setup is not working correctly?

I also found some mistakes in Figure 58. First WREG CONFIG3 should be 0xC0 not 0x80. Second that WREG CONFIG2 shuld be 0x30 not 0x10.

  • 0
    TI__Mastermind 38745 points
    Hey Arash,

    You are seeing typical behavior. DRDY will only go high in the falling edge of SCLK or just prior to new data being ready. In this image you are seeing DRDY stay low because data is not read, then go high 4*tclk before data is about to be ready again, and then transition low to indicate that a new sample is ready. If you are reading data with each DRDY, DRDY will come high right when you begin to read data and only go low again the next time data is ready.

    Regards,
    Brian