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ADS1178: ADS1178 SCLK/fCLK for Frame-Sync Format

yoshiki hasebe
Mastermind 6385 points
Part Number: ADS1178

Dear Sirs,

My customer asked us about SCLK/fCLK for Farme-Sync of ADS1178.

There is a description of the following 13 page of the data sheet.

(2) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK.

On the other hand, there is the following description in the 18 page of the data sheet.

The number of SCLKs within a frame period (FSYNC clock) can be any power of two 

ratio of clock cycles (1, 1/2, 1/4, etc.), as long as the number of cycles is sufficient to shift the data output

 

(4)In addition, on SPI 7 page of the data sheet has the following description.)

For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc.

from all channels within one data frame.

Then Question is SCLK / fCLK in Frmae-Sync format Why "Must"?

What is the difference between SCLK / fCLK notation in SPI and Frame-Sync?

By the way, my customer is using 1/16 in Frame-Sync format.

Best Regards,

Y.Hasebe

  • 0
    TI__Guru 57296 points
    Hello Yoshiki-san,

    Thanks for your post!

    The reason that the SCLK must equal a 1/2^n ratio of CLK in FSYNC Mode is that Frame-Sync is a continuous interface. This means that both the CLK and SCLK signals must be continuously running. If the SCLK frequency was a non- 1/2^n ratio of CLK, you would eventually run into a condition that caused you to miss data, either at the beginning or at the end of the data word.

    The more traditional SPI interface does not require a continous SCLK - in fact, you can send the SCLK signals in "bursts," so long as you send enough clocks to read all the data bits before the next sample is ready.

    In both modes, keeping SCLK/CLK to a 1/2^n ratio yields the best noise performance, but any other clock frequency will still allow the device to perform within the min/max specifications.

    Best Regards,
  • 0 in reply to Ryan Andrews
    Mastermind 6385 points

    Hello Ryan-san,

    Thank you for your quick reply.

    I understood that there is no problem if 2 ^ N in FSYNC mode.
    (That is, even 1/16 of the customer specification does not matter)
    Is this correct?

    In the datasheet there is no entry listed up to 1/8.
    Is there reason for limiting up to 1/8 of the data sheet?

    Best Regards,

    Y.Hasebe

  • 0 in reply to yoshiki hasebe
    TI__Guru 57296 points
    Hello Yoshiki-san,

    Yes, the customer specification is fine for SCLK/CLK ratio of 1/16. The datasheet does not limit the ratio up to 1/8, we put the "etc." to indicate that the pattern continues. :)

    Also verify that the Frame-Sync Timing Requirements are satisfied.

    Best Regards,
  • 0 in reply to Ryan Andrews
    Mastermind 6385 points

    Hello Ryan-san,

    Thank you for your reply.

    I understand your comment.

    I will answer to my customer it.

    Best Regards,

    Y.Hasebe