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DAC8750: Software reset

Part Number: DAC8750

Hello.

The datasheet says:

8.6.1.4 Reset Register
The DACx750 reset register is written to at address 0x56. Table 17 provides the description.

Table 17. Reset Register
DATA BIT(S): DB0
NAME: RESET
DEFAULT: 0
DESCRIPTION: Software reset bit. Writing 1 to the bit performs a software reset that resets all registers and the ALARM status to the respective power-on reset default value. After reset completes, the RESET bit clears itself.


Question:
How long does it take to complete the reset after writing 0x01 to the reset register?


Best Regards.

  • Sato-san,

    The precise timing is a bit difficult to define, however the reset is very nearly instantaneous as far as the digital mechanisms are concerned. In the digital domain the various control gates would be reset on the order of microseconds. In the analog domain, it may take more time for the reference and analog outputs to power-down to zero-scale compared to the digital content but this is dependent on loading conditions and it would not have any impact on the reset timing of the digital content.

  • Thank you for your answer.
    For example, can I reset in the following sequence?

    1. Write 0x0001 to the reset register(0x56).
    2. Immediately write to the NOP(0x00_0000).
    3. Write 0x0028 to the configuration register(0x57).

  • Sato-san,

    I apologize for the delay in my response. I have been off-site.

    I believe your timing should be okay. Please let us know your results.

  • Hi,

    Please do the same question from me.
    Indicators to be designed are required.

    Q1: After setting 0x01 to address 0x56,
        how long will it take for the register to clear and complete the reset?

        In other words, how long does it take to set "1" RESET Bit to return "0"? ("0"→ "1")

        If it can not be expressed in numerical time,
        it can be said to say reset completion after several pulses in SCLK?.

    Q2: When 0x01 is set to address, 0x56, is the Shift Register for serial communication cleared?

    best regards

  • cafain said:

    Q1: After setting 0x01 to address 0x56,
        how long will it take for the register to clear and complete the reset?

        In other words, how long does it take to set "1" RESET Bit to return "0"? ("0"→ "1")

    As I said - this is somewhat difficult to define because, at least by my understanding, the operation should be nearly instantaneous so it would happen faster than you could possibly read it back. Actually measuring this with physical silicon isn't really possible because the operation is faster than you can read the register.

    cafain said:
    Q2: When 0x01 is set to address, 0x56, is the Shift Register for serial communication cleared?

    I am not sure about this, I would need to ask someone from our digital design group to simulate this. Why is this of interest?

  • Hi, Kevin-san

    I appreciate your detailed explanation.

    I realized that it is not realistic to use this time as design data because the time to complete the reset is the moment (which is faster than several ns!?).

    It is the background that I asked questions of Q2,
    From the question of Q1, if you want to transmit the next data without waiting time if the waiting time is short (for example 40 μs), if you want to send the next data, consider sending NOP and adding time intend to do something.

    please reply.

    best regards

    cafain

  • Kevin-san,

    As well as me, the defined reset time is required.
    Should I wait 1 microsecond or wait 10 microseconds?
    Please define a sufficient waiting time.

    ---
    Q2: When 0x01 is set to address, 0x56, is the Shift Register for serial communication cleared?
    ---
    For example,
    I want to set the configuration register immediately after writing to the reset register.

    If the reset time is 46 microseconds,
    When cleared, the shift register after communication becomes 0x000000.
    If not cleared, the shift register after communication becomes 0x570028.

  • Howdy cafain,

    To help clarify this question. Have you been able to reference the DAC8750 datasheet timing specifications? As long as these conditions are met you should expect correct write and read operations.

    The rising edge of the latch pin correctly latches the written data to internal registers, when pulling up the latch pin please verify that it satisfies the minimum high time, reported in page 9 of the DS, of 40ns. After this time elapses, the latch pin can be pulled low to start the next write transaction.

    The timing requirements slightly differ between write and read mode, so please verify that these conditions are met when writing or reading to the device at fast speeds.

    Best Regards,
    Matt