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Tool/software: Code Composer Studio
Fellow I have some problems with a integration of ADS1292R with msp432, can anyone give me some help.
Hi Ryan,
I am developing a prototype of electrocardiogram with recourse to the front end ads1292R, I bought the chip and started to assemble the entire circuit from root, I am using the msp432 micro controller. Now I am facing serious problems, I have already created the spi drivers, but I would like to have a functional example, or at least one guide line, to check the ads1292R communication with the microcontroller, I created a main file, but I do not know how call the ads1292R startup, or check conversion values. I send you my SPI files:
/*****************************************************************
* INCLUDE *
******************************************************************/
#include <msp.h>
#include "ads1292r.h"
/*****************************************************************
* GLOBAL VARIABLES *
******************************************************************/
unsigned char ADC_READ_DATA[16];
unsigned char ADS1292R_SPI_CMD_FLAG = 0;
unsigned char ADS1292R_SPI_DATA_FLAG = 0;
unsigned char SPI_SEND_COUNT = 0;
unsigned char SPI_TX_COUNT = 0;
unsigned char SPI_TX_BUFF[10];
unsigned char SPI_RX_DATA_FLAG = 0;
unsigned char SPI_RX_BUFF[12];
unsigned char SPI_RX_COUNT = 0;
unsigned char SPI_RX_EXP_COUNT = 0;
unsigned char ECG_DATA_READY;
long ADS1292R_ECG_DATA_BUFF[6];
/*DEFINE RECORD STATE OF ECG*/
/**/
#define DELAY_COUNT 2
extern struct ADS1292R_STATE ecg_Record_State;
extern unsigned char ECG_RECORD_DATA_BUFFER[256], RECORD_H;
unsigned char ADS1292R_REGVAL[16] = {
/*DEVICE ID*/
0x00,
/*CONFIG1*/
0x02,
/*CONFIG2*/
0xE0,
/*LOFF*/
0xF0,
/*CH1SET (PGAIN = 6)*/
0x00,
/*CH2SET (PGAIN = 6)*/
0x00,
/*RLD_SENS (DEFAULT)*/
0x2C,
/*LOFF_SENS (DEFAULT)*/
0x0F,
/*LOFF_STAT*/
0x00,
/*RESP1*/
0xEA,
/*RESP2*/
0x03,
/*GPIO*/
0x0C
};
unsigned char ADS1292R_DEFAULT_REGISTERS_SETTINGS[15] = {
/*DEVICE ID*/
0x00,
/*CONFIG1*/
0x02,
/*CONFIG2*/
0xE0,
/*LOFF*/
0xF0,
/*CH1SET (PGAIN = 6)*/
0x00,
/*CH2SET (PGAIN = 6)*/
0x00,
/*RLD_SENS (DEFAULT)*/
0x2C,
/*LOFF_SENS (DEFAULT)*/
0x0F,
/*LOFF_STAT*/
0x00,
/*RESP1*/
0xEA,
/*RESP2*/
0x03,
/*GPIO*/
0x0C
};
/*****************************************************************
* VARIABLES FOR SPI INTERATION *
******************************************************************/
void ads1292R_Clock_Select(unsigned char clock){
if(clock == 1){
P4->OUT |= (enum PORT4_ADC_CONTROL)ADC_CLK_SEL;
}else{
P4->OUT &= ~(enum PORT4_ADC_CONTROL)ADC_CLK_SEL;
}
}
/**********ADS1292R RESET**********/
void ads1292R_Reset(void){
unsigned short i;
P3->OUT |= (enum PORT3_ADC_CONTROL)ADC_RESET; /*SET PIN TO HIGH*/
/*PROVIDE A DELAY*/
for( i = 0; i < 5000; i++); /*WAIT SOME TIME*/
P3->OUT &= ~(enum PORT3_ADC_CONTROL)ADC_RESET; /*SET PIN TO LOW*/
for( i = 0; i < 5000; i++); /*WAIT SOME TIME*/
P3->OUT |= (enum PORT3_ADC_CONTROL)ADC_RESET; /*SET PIN TO HIGH*/
for( i = 0; i < 35000; i++);
}
/**********ADS1292R DISABLE START**********/
void ads1292R_Disable_Start(void){
unsigned short i;
P3->OUT &= ~(enum PORT3_ADC_CONTROL)ADC_START; /*SET PIN TO LOW*/
/*PROVIDE A DELAY*/
for( i = 0; i < 35000; i++); /*SMALL DELAY*/
}
/**********ADS1292R ENABLE START**********/
void ads1292R_Enable_Start(void){
unsigned short i;
P3->OUT |= (enum PORT3_ADC_CONTROL)ADC_START; /*SET PIN TO HIGH*/
/*PROVIDE A DELAY*/
for( i = 0; i < 50000; i++); /*SMALL DELAY*/
}
/**********ADS1292R CHIP ENABLE**********/
void ads1292R_ChipSet_Enable(void){
/*ADS1292R CS PIN IS IN ACTIVE LOW*/
P3->OUT &= ~(enum PORT3_ADC_CONTROL)ADC_CS; /*SET TO LOW*/
}
/**********ADS1292R CLEAR CHIP ENABLE**********/
void ads1292R_ChipClear_Enable(void){
unsigned char CsDelay;
for(CsDelay = 0; CsDelay <100; CsDelay++);
/*ADS1292R CS PIN IS IN ACTIVE LOW*/
P3->OUT |= (enum PORT3_ADC_CONTROL)ADC_CS; /*SET TO HIGH*/
}
/**********ADS1292R DRDY INTERRUPT**********/
void ads1292R_DRDY_Interrupt(void){
P2->DIR &= ~0x02;
P2->REN |= BIT5; /*ENABLE P2.5 INTERNAL RESISTANCE*/
P2->OUT |= BIT5; /*SET P2.5 AS PULL-UP RESISTANCE*/
P2->IES |= BIT5; /*P2.5 LO/HI EDGE*/
P2->IFG &= ~BIT5; /*P2.5 IFG CLEARED*/
P2->IE &= ~BIT5; /*P2.5 INTERRUPT DISABLE*/
}
/**********ENABLE ADS1292R DRDY INTERRUPT**********/
void Enable_ads1292R_DRDY_Interrupt(void){
P2->IFG &= ~BIT5; /*P2.5 IFG CLEARED*/
P2->IE |= BIT5; /*P2.5 INTERRUPT ENABLE*/
}
/**********DISABLE ADS1292R DRDY INTERRUPT**********/
void Disable_ads1292R_DRDY_Interrupt(void){
P2->IFG &= ~BIT5; /*P2.5 IFG CLEARED*/
P2->IE &= ~BIT5; /*P2.5 INTERRUPT ENABLE*/
}
void Set_ads1292R_GPIO(void){
P4->SEL0 = 0x00;
P4->DIR |= 0x8F;
P4->OUT |= (enum PORT4_ADC_CONTROL)POW_CE;
P3->DIR |= 0x07;
P3->OUT &= 0xF8;
P3->OUT |= (enum PORT3_ADC_CONTROL)ADC_CS; // Set RESET, START to Low and CS to High
P3->OUT |= (enum PORT3_ADC_CONTROL)ADC_RESET; // Set RESET, START to Low and CS to High
P4->OUT = 0x03;
//dataCnt = 0; // P1.1 interrupt disabled
}
/**********SET ADS1292R UCB0_SPI**********/
void Set_ads1292R_UCB0_SPI(void)
{
P3->SEL0 |= BIT5 | BIT6 | BIT7; /*SET 3 PIN SPI PERIPHERAL BITS*/
P3->DIR |= BIT5 | BIT6; /*CLOCK AND DIROUT AS OUTPUT*/
P3->DIR &= ~BIT7; /*DIN AS INPUT*/
EUSCI_B0->CTLW1 |= EUSCI_B_CTLW0_SWRST; /*ENABLE SW RESET*/
EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_MSB | EUSCI_B_CTLW0_MST | EUSCI_B_CTLW0_SYNC;
//[b2-1] 00- 3-pin SPI
//[b3] 1 - Master mode
//[b4] 0 - 8-bit data
//[b5] 1 - MSB first
//[b6] 0 - Clock polarity low.
//[b7] 1 - Clock phase - Data is captured on the first UCLK edge and changed on the following edge.
EUSCI_B0->CTLW1 |= TASSEL__ACLK; // ACLK
UCB0BR0 = 24; // 1 MHz
UCB0BR1 = 0; //
EUSCI_B0->CTLW1 &= ~EUSCI_B_CTLW0_SWRST; /*CLEAR SW RESET, RESUME OPERATION*/
}
/**********SET ADS1292R DMA**********/
void Set_DMA_SPI(void)
{
DMACTL0 = DMA0TSEL_12; // USCI_B0 Transmit Ready Trigger
//DMA0SA = (void (*)())&UCB0RXBUF; // Source block address
//DMA0DA = (void (*)())ADC_Read_data; // Destination single address
DMA0SZ = 16; // Block size
DMA0CTL = DMADT_4 + DMADSTINCR_3 + DMADSTBYTE + DMASRCBYTE;
// Rpt, inc src, byte-byte
DMA0CTL |= DMAEN; // Enable DMA for consecutive Xfers
}
/**********ADS1292R SPI COMMAND DATA**********/
void ads1292R_SPI_Command_Data(unsigned char data_in){
unsigned char delayVar;
ads1292R_ChipSet_Enable();
for(delayVar = 0; delayVar < 50; delayVar++);
ads1292R_ChipClear_Enable();
ads1292R_ChipSet_Enable();
EUSCI_B0->TXBUF = data_in;
while((EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG0));
delayVar = EUSCI_B0->RXBUF;
for (delayVar = 0; delayVar < 150; delayVar++);
}
/**********ADS1292R WAKE UP**********/
void ads1292R_WakeUp(void){
ads1292R_SPI_Command_Data(WAKEUP); /*SEND WAKE UP COMMAND */
}
/**********ADS1292R SLEEP**********/
void ads1292R_Sleep(void){
ads1292R_SPI_Command_Data(STANDBY); /*SEND STANDBY COMMAND */
}
/**********ADS1292R SOFT START**********/
void ads1292R_Soft_Start(void){
ads1292R_SPI_Command_Data(START); /*SEND START COMMAND */
ads1292R_ChipClear_Enable();
}
/**********ADS1292R START/RE-START**********/
void ads1292R_HardReStart(void){
P3->OUT |= (enum PORT3_ADC_CONTROL)ADC_START;
}
/**********ADS1292R SOFT RESET**********/
void ads1292R_Soft_Reset(void){
ads1292R_SPI_Command_Data(RESET); /*SEND RESET COMMAND */
}
/**********ADS1292R SOFT STOP**********/
void ads1292R_Soft_Stop(void){
ads1292R_SPI_Command_Data(STOP); /*SEND STOP COMMAND */
}
/**********ADS1292R HARD STOP**********/
void ads1292R_Hard_Stop (void){
unsigned short i, j;
P3->OUT &= ~(enum PORT3_ADC_CONTROL)ADC_START; /*SET START PIN TO LOW*/
for (j = 0; j < DELAY_COUNT; j++){
for ( i=0; i < 35000; i++);
}
}
/**********ADS1292R START READ CONTINUOUS**********/
void ads1292R_Start_Read_Data_Continuous (void){
ads1292R_SPI_Command_Data(RDATAC);
}
/**********ADS1292R STOP READ CONTINUOUS**********/
void ads1292R_Stop_Read_Data_Continuous (void){
ads1292R_SPI_Command_Data(SDATAC);
}
/**********ADS1292R START DATA CONVERTION COMMAND**********/
void ads1292R_Start_Data_Conv_Command (void){
ads1292R_SPI_Command_Data(START);
}
/**********ADS1292R INITIALIZATION**********/
void ads1292R_Init(void){
ads1292R_Reset();
ads1292R_Disable_Start();
ads1292R_Enable_Start();
}
/**********ADS1292R ENABLE CONVERTION**********/
void ads1292R_EnableConvertion(void){
ads1292R_Start_Read_Data_Continuous();
ads1292R_HardReStart();
}
/**********ADS1292R REGISTERS WRITE**********/
void ads1292R_Reg_Write(unsigned char READ_WRITE_ADDRESS, unsigned char DATA){
short y;
switch(READ_WRITE_ADDRESS){
case 1:
DATA = DATA & 0x87;
break;
case 2:
DATA = DATA & 0xFB;
DATA |= 0x80;
break;
case 3:
DATA = DATA & 0xFD;
DATA |= 0x10;
break;
case 7:
DATA = DATA & 0x3F;
break;
case 8:
DATA = DATA & 0x5F;
break;
case 9:
DATA |= 0x02;
break;
case 10:
DATA = DATA & 0x87;
DATA |= 0x01;
break;
case 11:
DATA = DATA & 0x0F;
break;
default:
break;
}
SPI_TX_BUFF[0] = READ_WRITE_ADDRESS | WREG;
SPI_TX_BUFF[1] = 0; /*WRITE SINGLE BYTE*/
SPI_TX_BUFF[2] = DATA; /*WRITE SINGLE BYTE*/
ads1292R_ChipSet_Enable();
for ( y = 0 ; y < 50; y++);
EUSCI_B0->TXBUF = SPI_TX_BUFF[0]; /*SEND THE FIRST DATA TO TX BUFFER*/
while((EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG0)); /*EUSCI_B0_ TX READY?*/
y = EUSCI_B0->RXBUF; /*READ RX BUFF*/
EUSCI_B0->TXBUF = SPI_TX_BUFF[1]; /*SEND THE FIRST DATA TO TX BUFFER*/
while((EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG0)); /*EUSCI_B0_ TX READY?*/
y = EUSCI_B0->RXBUF; /*READ RX BUFF*/
EUSCI_B0->TXBUF = SPI_TX_BUFF[2]; /*SEND THE FIRST DATA TO TX BUFFER*/
while((EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG0)); /*EUSCI_B0_ TX READY?*/
y = EUSCI_B0->RXBUF; /*READ RX BUFF*/
}
/**********ADS1292R REGISTERS READ**********/
unsigned char ads1292R_Reg_Read (unsigned char READ_ADDRESS){
unsigned char retVal; /*RETURN VALUE*/
SPI_TX_BUFF[0] = READ_ADDRESS | RREG;
SPI_TX_BUFF[1] = 0; /*READ BYTE NUMBER -1*/
ads1292R_ChipSet_Enable(); /*SET CHIP SELECT TO LOW*/
EUSCI_B0->TXBUF = SPI_TX_BUFF[0]; /*SEND THE FIRST DATA TO TX BUFFER*/
while((EUSCI_B0->IFG & EUSCI_B_IFG_TXIFG0)); /*EUSCI_B0_ TX READY?*/
EUSCI_B0->TXBUF = SPI_TX_BUFF[1]; /*SEND THE FIRST DATA TO TX BUFFER*/
while((EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG0)); /*EUSCI_B0_ TX READY?*/
retVal = EUSCI_B0->RXBUF; /*READ RX BUFFER*/
EUSCI_B0->RXBUF = 0x00; /*SEND FIRST DATA TO THE TX BUFFER*/
while((EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG0)); /*EUSCI_B0_ TX READY?*/
retVal = EUSCI_B0->RXBUF; /*READ RX BUFFER*/
ads1292R_ChipClear_Enable(); /*DISABLE CHIP SELECT*/
return retVal; /*RETURN THE VALUE*/
}
/**********ADS1292R DEFAULT REGISTERS INITIALIZATION**********/
void ads1292R_DefaultReg_Init(void){
unsigned char regInit;
ads1292R_ChipSet_Enable();
for(regInit = 0; regInit<100; regInit++);
ads1292R_ChipClear_Enable();
if((ADS1292R_REGVAL[0] & 0x20 )==0x20){
for(regInit = 1; regInit<12;regInit++){
ads1292R_Reg_Write(regInit, ADS1292R_DEFAULT_REGISTERS_SETTINGS[regInit]);
}
}else{
for(regInit = 1; regInit<12;regInit++){
ads1292R_Reg_Write(regInit, ADS1292R_DEFAULT_REGISTERS_SETTINGS[regInit]);
}
}
}
/**********ADS1292R READ ALL REGISTERS**********/
void ads1292R_ReadAll_Reg(unsigned char ADS1292R_BUFF[]){
unsigned char AllReg_i;
ads1292R_ChipSet_Enable();
for(AllReg_i = 0; AllReg_i<200; AllReg_i++);
ads1292R_ChipClear_Enable();
for(AllReg_i = 0; AllReg_i<12; AllReg_i++){
ADS1292R_BUFF[AllReg_i] = ads1292R_Reg_Read(AllReg_i );
}
}
/**********ADS1292R POwer INIT**********/
void ads1292R_PowerOn_Init(void){
volatile unsigned short ini_i, j;
ads1292R_InitResource();
ads1292R_Reset();
for(j=0; j<DELAY_COUNT;j++){
for(ini_i = 0; ini_i < 20000; ini_i++);
for(ini_i = 0; ini_i < 20000; ini_i++);
for(ini_i = 0; ini_i < 20000; ini_i++);
}
ads1292R_DRDY_Interrupt();
ads1292R_Clock_Select(1); /*SET INTERNAL CLOCK*/
for(ini_i = 0; ini_i < 20000; ini_i++);
for(ini_i = 0; ini_i < 20000; ini_i++);
for(ini_i = 0; ini_i < 20000; ini_i++);
ads1292R_Disable_Start();
ads1292R_Enable_Start();
ads1292R_Hard_Stop();
ads1292R_Start_Data_Conv_Command();
ads1292R_Soft_Stop();
for(j=0; j<DELAY_COUNT;j++){
for(ini_i = 0; ini_i < 20000; ini_i++);
}
ads1292R_Stop_Read_Data_Continuous();
for(j=0; j<DELAY_COUNT;j++){
for(ini_i = 0; ini_i < 35000; ini_i++);
}
for(j=0; j<DELAY_COUNT;j++){
for(ini_i = 0; ini_i < 35000; ini_i++);
}
ads1292R_ReadAll_Reg(ADS1292R_REGVAL);
ads1292R_DefaultReg_Init();
ads1292R_ReadAll_Reg(ADS1292R_REGVAL);
}
void ads1292R_Parse_DataPacket(void){
unsigned char ecg_chan_num;
switch(ecg_Record_State.state){
case DATA_STREAMING_STATE:
{
for(ecg_chan_num = 0; ecg_chan_num < 3; ecg_chan_num++){
ADS1292R_ECG_DATA_BUFF[ecg_chan_num] = (signed long)SPI_RX_BUFF[3*ecg_chan_num];
ADS1292R_ECG_DATA_BUFF[ecg_chan_num] = ADS1292R_ECG_DATA_BUFF[3*ecg_chan_num] << 8;
ADS1292R_ECG_DATA_BUFF[ecg_chan_num] |= SPI_RX_BUFF[3*ecg_chan_num+1];
ADS1292R_ECG_DATA_BUFF[ecg_chan_num] = ADS1292R_ECG_DATA_BUFF[3*ecg_chan_num] << 8;;
ADS1292R_ECG_DATA_BUFF[ecg_chan_num] |= SPI_RX_BUFF[3*ecg_chan_num+2];
}
}
break;
case ACQUIRE_DATA_STATE:
case ECG_RECORDING_STATE:
{
unsigned char *ptr;
ptr = &ECG_RECORD_DATA_BUFFER[RECORD_H << 3]; /*POINT TO CIRCULAR BUFFER AT HEAD*8 */
*ptr++ = SPI_RX_BUFF[0]; /*STORE STATUS*/
*ptr++ = SPI_RX_BUFF[1]; /*STORE STATUS*/
/*SPI_RX_BUFF IS ALWAYS 0x00 DO IT IS DISCARDED*/
*ptr++ = SPI_RX_BUFF[3]; /*CH0 [23-16] = MSB (24 BIT DEVICE)*/
*ptr++ = SPI_RX_BUFF[4]; /*CH0 [15-08] = MID (24 BIT DEVICE)*/
*ptr++ = SPI_RX_BUFF[5]; /*CH0 [07-00] = LSB (24 BIT DEVICE)*/
*ptr++ = SPI_RX_BUFF[6]; /*CH1 [23-16] = MSB (24 BIT DEVICE)*/
*ptr++ = SPI_RX_BUFF[7]; /*CH1 [15-08] = MID (24 BIT DEVICE)*/
*ptr++ = SPI_RX_BUFF[8]; /*CH1 [07-00] = LSB (24 BIT DEVICE)*/
RECORD_H++; /*INCREMENT CIRCULAR BUFFER POINTER*/
if(RECORD_H == 32) /*CHECK FOR CIRCULAR BUFFER DEPTH*/
RECORD_H = 0; /*REST ONCE IT REACH TO MAX*/
}
break;
default:
break;
}
}
void ads1292R_Parse_Data_Packet(void){
if((ADS1292R_REGVAL[0] & 0x03) == ADS1292_24BIT){
ads1292R_Parse_Data_Packet();
}
ECG_DATA_READY = 1;
}
void ads1292R_Device_Out_Bytes(void){
if((ADS1292R_REGVAL[0] & 0x03) == ADS1292_24BIT){
SPI_RX_EXP_COUNT = 9; /*3 BYTE STATUS + 3 BYTES CH1 DATA + 3 BYTES CH0 DATA*/
}
}
