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ADS1293: CLK pin is output in reset state

Part Number: ADS1293

I have designed an ADS1293 with an external 400kHz oscillator. The oscillator starts with VDDIO from the ADS1293 and is connected to the CLK pin. The fist samples had a problem. I saw a suppressed clock signal when the ADS1293 was in reset state. I added a series resistor and I find out that the CLK pin of the ADS1293 is configured as output. But the datasheet says that EN_CLKOUT is disabled. 0: Clock output driver disabled (default) 

After configure the oscillator control register it behaves as expected.

Can anyone explain the behavior?

An other question according to the ADS1293 clock generation. The datasheet doesn't say how to terminate the XTALx pins if the internal oscillator isn't used. Can it be left floating?

Kind regards

Sven

  • Hello Sven,

    Thanks for your post!

    You are correct that the CLK pin should be configured as an input by default. I have yet to find anything to the contrary in any other documentation so far. If you read from the registers before configuring, does the EN_CLKOUT bit read high or low? Are you able to write to the registers consistently while your CLK input signal is still attenuated?

    I believe the XTALx pins can be left floating. Again, it appears this was not documented very well. For that I apologize. I'll see if I can find out more and if I learn anything different, I will let you know.

    Best Regards,
  • Hello Ryan,

    I have done additional test. I can read and write any registers without a valid clock input. BTW the amplitude is around 100mV with a series resistor of 1.2 kOhm. After setting the reset pin (RSTB) to high I read the RefID resister to check the SPI interface works. After that I have read the OSC_CN register. The content is 0x00 as expected. Then I have written all combinations of SHDN_OSC and EN_CLKOUT with the following results:

    • EN_CLKOUT=0, SHDN_OSC=0 => CLK has low impedance
    • EN_CLKOUT=1, SHDN_OSC=0 => CLK has low impedance
    • EN_CLKOUT=0, SHDN_OSC=1 => CLK has high impedance
    • EN_CLKOUT=1, SHDN_OSC=1 => CLK has high impedance

    It seems that the EN_CLKOUT bit has no effect. Figure 27 in the datasheet isn't correct.

    King regards

    Sven

  • Hi Sven,

    Thank you for the feedback. When I get a chance, I will try to replicate the same test on the bench. If necessary, I will add your feedback to our notes for the next datasheet update.

    Best Regards,
  • Hello Sven,

    Sorry for the delay, but I did finally have a chance to test this on our ADS1293EVM. The only condition which produced a low input impedance on the CLK pin was when EN_CLKOUT = 1, SHDN_OSC = 0. When that happened, the external CLK amplitude reduced from 3.3 Vpp to about 2 Vpp. I did not have an external resistor in series and the function generator output was set to High-Z.

    When EN_CLKOUT = 1 and SHDN_OSC = 0, the bottom buffer in Figure 27 will be enabled and try to overdrive the CLK pin. As long as that buffer is disabled (i.e. if either EN_CLKOUT = 0 or SHDN_OSC = 1), then the external clock source connected to the CLK pin should see a high impedance. If SHDN_OSC = 1, then the state of EN_CLKOUT does not have any impact.

    Best Regards,

  • Hello Ryan,

    thank you very much for the support. If I understand you right the behavior on you EVM is as expected. This is very strange. Maybe I have a problem with the chip. It was the first prototype and I had a problem with the ADS1293. On the first prototype the XTAL1 was shorted to GND. But this caused a very high supply current. This may damaged the chip (only a part) on the first board. Next week I get new boards and I check the behavior of the CLK pin again.

    BTW: Do you have any news for me how to terminate unused XTALx pins? 

    Kind regards

    Sven

  • Hello Ryan,

    I did additional test with new boards and I have the same behavior. During the tests I was surprised that the CLK pin changed the behavior from low impedance to high impedance in reset state and the host controller was stopped in the debug session. This gave me the idea that the ADS oscillator mus be clocked at least one time for initialization. So I added a a short cable at the XTAL2 pin and it works as expected. The noise on the cable produces some clocks. If the XTAL2 pin is connected to GND or left unconnected the CLK input pin has low impedance in reset state. 

    To reproduce the behavior I described prior you must short the XTAL2 pin to ground. 

    Kind regards

    Sven