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ADS8588S: Initiating a new conversion when the data read from the last conversion is not complete.

Part Number: ADS8588S

What is the result if a new conversion is initiated with the ADS8588S prior to completing the read operation from the last conversion?  I ask this to understand the potential effects of a momentarily corrupted SPI serial clock.  I am trying to determine how the SPI master and the ADS8588S can be resynced after such an event.

  • Hello John
    We are looking into this and will respons soon

    Regards,
    Cynthia
  • Hello John

    The device allows for reading data while a new conversion is occurring, as well as no conversion. Shown in Figure 2 (below) of the datasheet there is a minimum time between the rising edge of CS and falling edge of Busy of 40 ns.

    The device should not be operated where CS is low, reading data, while BUSY is going through a transition. This can corrupt data.

    To make sure data is correct when a resync has occurred, the device can be reset, or an initial dummy conversation signal can be sent.

    Regards

    Cynthia

  • Cynthia,

    Thank you for your reply.  Unfortunately, the answer to my question remains unclear to me.  The datasheet states that CS may be held low for a multi-channel read operation or may be cycled in between each 2-byte read of a single channel's data.  My question is not related to taking CS low during a conversion or at a transition of BUSY.  Rather, I need to know what the response is if a new conversion is initiated before all of the data from the previous conversion (currently held in the read buffers) has been read.  For instance, a full read cycle requires 128 SCLK cycles after CS is taken low.  What happens if only 127 (or say 59) cycles of SCLK are received during the read operation, when CS is low and then a new conversion is initiated? 

    My concern is to understand if the entire read operation of the previous data has not been completed, will initiating a new conversion reset the data output shift register to point to the first bit of the new data set.  In other words, if something corrupts SCLK during a read operation and 128 bits have not been shifted out, CS goes high and then later another conversion is initiated, will the output shift register be reset to point to the first bit of the new data, when the new data is ready?  I guess another way of posing the question is: Does initiating a new conversion reset the output shift register and overwrite all older data whether the old data was unread or only partially read prior to the new data being ready?  I hope these attempts at describing what I am trying to understand are helpful.  I appreciate your help and look forward to your reply.

    J. Gordon

  • Cynthia,

    I thought of a simpler scenario to use to pose my question. What happens is I am only interested in the data from channel 1 and so terminate the read operation without reading the data for any additional channels - If I then initiate a new conversion, when busy returns to low will the first data output in a new read operation be the new data from channe1?

    J. Gordon
  • Hi John,

    Thanks for considering TI SAR ADC, let me explain to you, we have to divide it into different situations to discuss.

    As you know, ADS8588S' BUSY is an active-high digital output signal, this pin goes to logic high after the rising edges of both the CONVSTA and CONVSTB signals, indicating that the front-end, track-and-hold circuits for all input channels are in hold mode and that the ADC conversion has started, also the output data can be read when BUSY is high (Read During Conversion) or BUSY is low (Read After Conversion). Another important thing is, ADS8588S only updates the internal data registers with the conversion data for all analog channels at the end of conversion phase (when BUSY goes low), the data in internal data registers is kept before this moment.

    Read During Conversion:

    When the BUSY signal is high, any activity on the CONVSTA or CONVSTB inputs has no effect on the device. The BUSY output remains high until the conversion process for all channels is completed and the conversion data are latched into the output data registers for read out. This means, any new conversion during ongoing conversion and the data reading will not have any impact to the data read, the host controller still gets entire conversion results for the previous sample, also no new data caused by this new conversion initiated on CONVSTA or CONVSTB is updated into data registers because it has been ignored by device.

    Read After Conversion:

    Case 1:     the new conversion initiated on CONVSTA or CONVSTB (red BUSY high in figure 1 as below) is NOT finished during this data read.

    This data reading will not be affected by this new conversion because the data in the internal data registers is not updated with the new conversion data by this new conversion until the end of conversion phase (when red BUSY goes low).

    Case 2:     the new conversion initiated on CONVSTA or CONVSTB (red BUSY high in figure 2 as below) is finished during this data read.

    The new conversion data by this new initiated conversion will be updated into the internal data registers at the end of conversion phase (when red BUSY goes low), so host controller retrieves the data for some bits of previous conversion before this moment, also will retrieve the data for some bits of new initiated conversion after this moment. This is not a complete data and probably not correct.

    I hope this is helpful to you. Thanks.

    Best regards

    Dale

  • Thank you Dale. Your reply re-enforced the understanding I developed from studying the datasheet.

    However, my question regarding the resetting of the output shift register pointer still remains. When BUSY goes low and the data registers are updated, does the output shift register pointer reset to point to the first bit of the new channel 1 data? If so does this happen regardless of the state of CS? In your case 2, described above, will the read in progress during the BUSY transition from high to low stop receiving the next bit in line of the old data and begin receiving the first bit of the new data from channel1 on the next edge of SCLK?

    I am asking this to verify that it is not necessary to complete an entire 8-channel read operation prior to BUSY transitioning low and new data being placed in the data registers. I am not asking because I intend to purposefully hold CS low while BUSY transitions to low.

    I look forward to your reply and the further insight you might be able to provide.

    Best Regards,

    J. Gordon
  •  

    Hi John,

    Here are answers:

    does the output shift register pointer reset to point to the first bit of the new channel 1 data? 

    Answer:  I don't think so, because the data read is controlled by the host with /RD or /CS pulses for parallel or SCLK for serial,  the data read can be implemented Read During Conversion or Read after Conversion. I would like to double check with design team early next week and feedback to you.

    In your case 2, described above, will the read in progress during the BUSY transition from high to low stop receiving the next bit in line of the old data and begin receiving the first bit of the new data from channel 1 on the next edge of SCLK

    Answer:  the data reading will continue reading next bit of same data register but with new data in next bit, the data register is same data register.

    We always strongly recommend to finish all channel data reading either during BUSY high (Read During Conversion) OR during BUSY low (Read after Conversion), never read the data across the BUSY falling edge, because there is a higher risk to get incorrect data, this can be implemented perfectly by monitoring BUSY signal and controlling /RD and /CS signals.

     

    Best regards

    Dale

  • Hello Dale,

    As I stated earlier, I do not intend to extend any read operation across a BUSY falling edge. My concern is how I am going to gracefully recover if a corrupted signal causes a read operation to not actually issue 128 SCLK cycles that are registered by the device.

    If you can provide me a clear and accurate answer to the questions posed below, I think I will have what I need. Let's assume the following series of operations:

    1. RESET the ADC
    2. Initiate a conversion.
    3. Wait for a falling edge on BUSY.
    4. Read the channel 1 data using the SPI interface (CS, SCLK, DOUTA).
    5. Terminate the read operation by transitioning CS to high after reading only the first 16 data bits.
    6. Initiate a new conversion.
    7. Wait for a falling edge on BUSY.
    8. Read 16 bits of data using the SPI interface (CS, SCLK, DOUTA).

    The data from which channel will be read in step 8? Will it be the new (Step 6) data for channel 2 (meaning the shift register pointer DOES NOT reset when new data is loaded into the registers) or the new (Step 6) data for channel 1 (meaning the shift register pointer DOES reset)?

    Honestly, I am having a hard time believing the only way to return the shift register to the beginning of a data set is to precisely read all 128 data bits from the previous conversion or to the RESET the device. However, if that is the case I need to know that with absolute certainty, since that functionality will force me to RESET the device before each conversion.

    I look forward to your reply. I am getting a bit frustrated with this forum process to get a technical question answered. The cycle time is quite long and there is no way to get immediate feedback on if the question is well posed and well understood. I would welcome a phone call if you would be willing.

    J. Gordon
    GMH Engineering
    (801) 225-8970
    Mountain Time Zone
  • Hi John,

    We are  checking with design team and will get back to you tomorrow, thanks.

    Regards

    Dale

  • Hello John,

    I apologize for late feedback. Here are answers:

    "The data from which channel will be read in step 8?"   Answer:   Channel 1

    "Will it be the new (Step 6) data for channel 2 (meaning the shift register pointer DOES NOT reset when new data is loaded into the registers) or the new (Step 6) data for channel 1 (meaning the shift register pointer DOES reset)?"       Answer:   Channel 1, the data retrieving in step 8 is the new data for Channel 1.

    Once a busy fall is detected, the device will always reset itself to provide data from channel 1 and from the result of the new conversion. This is irrespective of which channel it was transmitting before busy fall.

    One more thing we would suggest you to use the FIRSTDATA pin which is there for the purpose of channel id syncing in case there is some doubt or confusion.

    Please also notice that When the BUSY signal is high, any activity on the CONVSTA or CONVSTB inputs has no effect on the device.

    We can have a call if this is still not clear for you, thanks.

    Best Regards

    Dale