ADS131A04: SPI Status Register indicates there are some errors

Dan Li62

Part Number: ADS131A04

Greeting!

I have come across with a problem when using ADS131A04. I use F28069 as a master controller and the SPI communication seems working. In my circuit, M2 is connected to GND; M1 is left unconnected; M0 is connected to IOVDD. This achieves a hamming code off, 16-bit device word, and asynchronous slave mode. Below is the screen shot after I check the STAT_M2 register.

But it has a problem with SPI. When I check STAT_S register, I get this response, ‭0010010100000011‬. From the instruction on Page 59, Bit 1 indicates that "CS is asserted or deasserted when SCLK is high" and Bit 0 indicates "Not enough SCLKs are sent per frame". Could you give some suggestions on how to solve these two errors?

Thanks for your time!

Dan

over 6 years ago

0 Tom Hendrick over 6 years ago

TI__Guru**** 168605 points

Hi Dan,

Are the glitches visible in your /CS captures to the ADS131A04 above real? Do you see them with an oscilloscope? If they are real, you will have to figure out what's causing the F28069 to toggle the line. For the second issue, how many active channels do you have setup in your configuration register?

0 Dan Li62 over 6 years ago in reply to Tom Hendrick

Intellectual 420 points

Hi Tom,

The glitches are shown in the oscilloscope. I am frustrated by these and I didn't see any reason in the code and circuit to cause these glitches in /CS.

For the second one, I haven't set the active channel. All the things are only in configuration stage.

Regards,
Dan

0 Tom Hendrick over 6 years ago in reply to Dan Li62

TI__Guru**** 168605 points

Hi Dan,

What are you using as the /CS input? Is it a GPIO? For the 'SCLKS per Frame', you have to keep in mind that the ADS131A04 considers the frame to be the entire sequence from the start of communication through the last channel of data. If the ADS131A04 is seeing the /CS glitch, that could cause the second error as well as the first.

0 Dan Li62 over 6 years ago in reply to Tom Hendrick

Intellectual 420 points

Hi Tom,

The CS input is GPIO. Regarding to the 'SCLKS per Frame', even if the ADC channels have not been enabled yet, every frame contains the response and all channel of data?

Thanks,

Dan

0 Tom Hendrick over 6 years ago in reply to Dan Li62

TI__Guru**** 168605 points

Hi Dan,

You can review section 9.5.1.2 of the ADA131A04 datasheet for more detail but, depending on how the device is configured, the frame size can include disabled channels. Have you been able to determine what was causing the glitches on your chip select input?

0 Tom Hendrick over 6 years ago in reply to Tom Hendrick

TI__Guru**** 168605 points

Hi Dan,

Have you resolved this issue?

0 Dan Li62 over 6 years ago in reply to Tom Hendrick

Intellectual 420 points

Hi Tom,

I still have these problems. But the chip can do the A2D conversion and transmit the data to the master MCU. So right now, I just leave the problems there.

0 Tom Hendrick over 6 years ago in reply to Dan Li62

TI__Guru**** 168605 points

Hi Dan,

Thank you for letting us know.

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ADS131A04: SPI Status Register indicates there are some errors