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DAC80004: Stand-Alone Timing

Josef Warta
Expert 3900 points
Part Number: DAC80004

Hello Team,

on page 8 of our datasheet you see a 'Stand-Alone Timing' (Figure 1).
There is a timing t19 mentioned which is used in two ways:

- between SDIN and SYNC line

- between CLR and VoutX

Is this correct?

Many Thanks

Josef

  • 0
    TI__Mastermind 46290 points
    Hello Josef,

    Thanks for pointing out the confusion, that is indeed a mistake on the datasheet.

    The correct utilization of the parameter is the one measuring the time-difference in between the falling edge of CLR and the response on VoutX. Meanwhile the case that is measured from the rising SCLK edge to falling SYNC edge should be represented by t20.

    We will rectify this in the datasheet quickly.
  • 0 in reply to Kevin Duke
    Prodigy 70 points

    Hi Josef, Hi Duke,

    thanks for answering my question. We suspected this fact. This wasnt the real subject for the qestion. It was only to keep apart the different timings. (t19 andt20)

    In the originial question we also asked about t20(Successive DAC Update).

    1.What is the minimum for this time?

    2. Do we need this time really? Do we have to be in time with it?

    3. We use the LDAC impulse to update all four channel at once!

    Do we have to wait this time after writing each channel or is it enough to be in time after writing the last of the four channels and use LDAC for updating?

    4. What do we need this time for? Are there any dependencies to the "Output voltage settling time" mentioned on page six of the datasheet?

    http://www.ti.com/lit/ds/symlink/dac80004.pdf

    Thanks

    vodi

  • 0 in reply to vodi
    TI__Mastermind 46290 points
    Hi Vodi,

    Very good questions. Knowing details concerning the internal implementation of the device, I believe again the author of the datasheet made a mistake there and the intention was for t20 to be a minimum.

    Essentially there is a sample and hold circuit implemented in the output stage in order to mitigate the observed code-to-code glitch energy and the complete sample, hold, and return to normal process for the circuit takes approximately 2.4us to complete.

    If you're updating different channels, this does not matter. This is only related to updating a single channel consecutive times. Furthermore if the time is violated the only thing you would really observe is that potentially you would not see the VOUT respond to one of the incremental writes. Basically if you wrote data, then 1us later wrote new data, you would never see the first data come to VOUT because the sample and hold circuit would be in the hold state.

    I hope that makes sense. Please let me know if we need to clarify more.

    I will work with the Systems Engineer to get the datasheet updated quickly.