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DAC80004: DAC80004

Part Number: DAC80004

Hello,

I'm trying to evaluate the DAC80004EVM and connect it to RPI3 module to SPI0.

I use python to control the DAC80004 but w/o success.

I'm not using signals CLR~ nor LDAC~

My code below:

import spidev
import time
import os,sys

spi = spidev.SpiDev()
spi.open(0,0)           # open bus 0, CE0.
spi.max_speed_hz = 976000

# CLR~   =1 => JP7=open
# LDAC~ =0 => Jp6=short

resp = spi.xfer([0x08,0x00,0x00,0x0f]) # Enable SDO
resp = spi.xfer([0x04,0xf0,0x00,0x0f]) # Power on
resp = spi.xfer([0x06,0xf0,0x00,0x0f]) # Update control by the 32 falling edge of sck
resp = spi.xfer([0x05,0x00,0x00,0x00]) # Cler Mode Reg zero scale
resp = spi.xfer([0x1d,0x00,0x00,0x00]) # Read Status Reg
resp = spi.xfer([0x0e,0x00,0x00,0x00]) # print('NOP Command')
print ('Status = {:02x}{:02x}{:02x}{:02x}'.format(resp[0],resp[1],resp[2],resp[3]))
resp = spi.xfer([0x14,0x00,0x00,0x00]) # Read Power Reg
resp = spi.xfer([0x0e,0x00,0x00,0x00]) # print('NOP Command')
print ('Power = {:02x}{:02x}{:02x}{:02x}'.format(resp[0],resp[1],resp[2],resp[3]))
resp = spi.xfer(0x03,0x0f,0xff,0x00) # Write to channel A the value 0xfff0

The Output of the device stuck at zero.

Please help.

Regards,

Asher

  • Asher,

    Your configuration of the !CLR and !LDAC pins sounds correct. Can you please also describe your hardware connections for providing power to the EVM as well as the configuration of JP1 and JP2? Perhaps a simple test would also be quickly toggling power with a different state on the POR pin controlled by JP3. With this in the 2-3 position the POR value should be mid-scale code. This way we can at least test if you have the analog signal chain in a healthy state and then move on to debugging the communication.

    I do not see how the SPI bus is configured in this code snippet. Maybe "open bus 0 and, CE0" means the clock polarity is 0 with the first edge as the critical edge (rising edge)? Looks like 976 kHz SCLK. The speed shouldn't be a problem and is actually quite slow so I do not feel like there is a timing nuances violating communication, however if my guess at the configuration of the clock polarity and phase is correct that may be where the problem is. Per the timing diagrams in the datasheet setup and hold times are measured against the falling SCLK edge, so the settings for polarity 0 clock should be CPOL = 0, CPHA = 1.

    Another means of debugging could be providing oscilloscope captures of the SPI transaction including the !SYNC, SCLK, and SDIN lines.
  • Thanks Kevin,

    I'll check all your suggestions and update.

    1. Regarding Power Down Mode register:
    xxx W/R | 0 1 0 0 | xxxx | xxxx | xxxx | xx PD1 PD0 | xxxx | Ch-D Ch-C Ch-B Ch-A --- Power up/down DAC n

    Do I have to write 4 times to this register? once for each Channel? to power it up
    For example
    a. 0x04, 0x00, 0x00, 0x01
    b. 0x04, 0x00, 0x00, 0x02
    c. 0x04, 0x00, 0x00, 0x04
    d. 0x04, 0x00, 0x00, 0x08

    or just once
    a. 0x04, 0x00, 0x00, 0x0f


    2. Regarding 4th register : Write to buffer and update DACn
    Assume pins: !LDAC=0 and !CLR=1
    Does writing to this 4th register (0x03....) immediatly change the DAC output?
    How does the LDAC register influence it?

    3. What is the minimum write operations required to operate the device in software mode, and to what registers?
    (Assume pins: !LDAC=0 and !CLR=1)?

    Thanks,
    Asher
  • Hello Asher,

    Asher Shtekel said:
    1. Regarding Power Down Mode register:
    xxx W/R | 0 1 0 0 | xxxx | xxxx | xxxx | xx PD1 PD0 | xxxx | Ch-D Ch-C Ch-B Ch-A --- Power up/down DAC n

    Do I have to write 4 times to this register? once for each Channel? to power it up
    For example
    a. 0x04, 0x00, 0x00, 0x01
    b. 0x04, 0x00, 0x00, 0x02
    c. 0x04, 0x00, 0x00, 0x04
    d. 0x04, 0x00, 0x00, 0x08

    or just once
    a. 0x04, 0x00, 0x00, 0x0f

    Writing just once to the register wtih 0x0F in the LSBs (writing logic high to all 4 Ch-X bits) should be sufficient.

    Asher Shtekel said:
    2. Regarding 4th register : Write to buffer and update DACn
    Assume pins: !LDAC=0 and !CLR=1
    Does writing to this 4th register (0x03....) immediatly change the DAC output?
    How does the LDAC register influence it?

    There are multiple modes of operation available for the LDAC mechanism which transfers data from the buffer register to the DAC data register. By default the LDAC register is configured to all 0's, meaning that all channels control their update mechanisms by the HW !LDAC signal. In this case, if !LDAC is tied to GND the device is operating in what is called "synchronous mode" meaning that all DAC data register writes are updated synchronously to the 32nd SCLK falling edge.

    Asher Shtekel said:
    3. What is the minimum write operations required to operate the device in software mode, and to what registers?
    (Assume pins: !LDAC=0 and !CLR=1)?

    In order to issue a clear command you would just write to the "Software clear" register with don't care data.

    For the LDAC functionality there are a few options with the !LDAC pin tied high. In this case you could either use the "Write to buffer n and update all DACs (software !LDAC" command, the "write to buffer and update DAC n" command, or you could write to the buffer followed by a separate write using the "update DAC n" command. You could also write a 1 to the respective channel registers in the "LDAC register" to internally tie LDAC low such that those channels behave in a synchronous manner.

    Essentially for a purely software defined interaction with the device the !LDAC and !CLR pins would be tied high and you would use the command mechanisms to provide this information.

    Let me know if you have further questions and the outcome of your tests from my previous post.

  • Thanks a lot,

    1. Found SCLK polarity issue - resolved.
    2. EVM schematics misleading Channel1 expected to be connect to A0+ but actually there is cross in the schematics, A0+ connected to VOUTB.
    3. I have a working code - below, But the problem is that only the first write load the DAC with the desired value (spi.xfer2([0x03,0x1f,0xff,0x00]) ) but not the second time till re-run the code. Any idea?
    If i change the value of the DAC and re-run it works fine but again only 1 write.

    import spidev
    import time
    import os,sys

    spi = spidev.SpiDev()
    #spi.open(0,0) will open bus 0, CE0.
    #spi.open(0,1) will open bus 0, CE1.
    #SPDIV.mode = 2
    spi.open(0,0)
    spi.max_speed_hz = 3900000
    # * `mode` - SPI mode as two bit pattern of clock polarity and phase [CPOL|CPHA], min: 0b00 = 0, max: 0b11 = 3
    spi.mode = 0b01

    # CLR~ = pull up
    # LDAC = 0

    print('Enable SDO')
    resp = spi.xfer2([0x08,0x00,0x00,0x02]) # Enable SDO
    print ('ResponseRead = {:02x} {:02x} {:02x} {:02x}'.format(resp[0],resp[1],resp[2],resp[3]))
    print()
    resp = spi.xfer2([0x14,0x00,0x00,0x00]) # Read Power Reg
    resp = spi.xfer2([0x0e,0x00,0x00,0x00]) # print('NOP Command')
    print ('Power = {:02x} {:02x} {:02x} {:02x}'.format(resp[0],resp[1],resp[2],resp[3]))

    resp = spi.xfer2([0x1d,0x00,0x00,0x00]) # Read Status Reg
    resp = spi.xfer2([0x0e,0x00,0x00,0x00]) # print('NOP Command')
    print ('Status = {:02x} {:02x} {:02x} {:02x}'.format(resp[0],resp[1],resp[2],resp[3]))
    high=0x10
    while True:
    resp = spi.xfer2([0x03,0x1f,0xff,0x00]) # write 0xfff0 to channel 1
    time.sleep(2)
    resp = spi.xfer2([0x03,0x10,0x00,0x00]) # write 0x0000 to channel 1
    time.sleep(2)


    Regards,
    Asher
  • Asher,

    Just looking at the code / deciphering the words you are sending the words appear to be accurate to the expected commands in your comments.

    Can you provide an oscilloscope capture of the bus transaction for the two consecutive writes to the DAC Data register?
  • Asher,

    Any updates on this thread?