Other Parts Discussed in Thread: LMP91200
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Hi Tom,
The traces below show the our SCLK, and CS signals, plus 5 consecutive SDO outputs.
The readings vary by a large amount (even though the voltage being sampled is steady) e.g. -0.056229, 0.136952, 0.087893, 0.119404
We get similar results bypassing the SPI hardware and "bit banging" the interface lines.
Likewise, varying the SCLK frequency - have tried from 1MHz up to 5MHz.
Cheers,
Graeme.
Hi Tom,
We're still debugging the problem but noise seems to be a factor. When we run the system off of battery the span of the consecutive measurements we get is more stable than if we have the system powered from a power brick. Still not as stable as we'd like, but averaging gives us a result that is good enough under battery power. We just need to see why it performs worse under other power situations.
We need to do more work on it.
Cheers,
Graeme.
HI Tom,
Not yet. We have performed some EMC testing and found the system to be noisy under certain circumstances, worse so with a DC power supply attached, so that EMC noise may be getting picked up by the measurement system and affecting the ADC stability too.
Its part of our ongoing investigation.
Cheers,
Graeme.
Tom Hendrick said:Hi Graeme,
Have you managed to resolve the issue?