Other Parts Discussed in Thread: ADS8361, TMS320F28377D
The ADS8363 Dual SAR ADC has a serial interface with a single CLK, single SDI, but dual SDO, one for each SAR ADC. The best way to interface this to a uC is not obvious, including the need for 20 clocks and detailed timing for ConvST and RD.
I have seen threads suggesting using two uC SPI ports, one as slave and one as Master, to drive a single clock and receive both SDO. I'm surprised to not see any reference design or schematic for what seems would be a common problem. I notice that Maxim and Analog Devices ADC's have similar 'multiple SDO' serial interfaces. The ADS8363 Mode bits appear to allow operation at half speed via a single SDO, which is probably the backup solution, but would be unfortunate.
Is it necessary/common to use a small FPGA to provide the detailed interface timing and provide a parallel interface or serial buffer? I've seen references to using the McBSP serial capability of the TMS320 series, but I don't see an equivalent capability in ARM devices.
I'm interested in using a STM32F723.
The Dual and Quad SPI services in ARM seem tantalizingly close. Is that the right approach?
Has this question been asked and answered somewhere that I haven't yet noticed? If so, apologies, and let's link to it here for others who stumble on the same issue.
Thanks very much for your guidance.
