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Original question:

ADS7947: Typical Input Driving Circuit ADS7947

ADS7947: Typical Input Driving Circuit ADS7947

Robbie Dinn
Prodigy 40 points
Part Number: ADS7947
Other Parts Discussed in Thread: TLE2027

Hello

I, like dale, am using a ADS7947 ADC. It is being used to replace an obsolete ADC (from another manufacturer) in some existing equipment. One of the requirements is that I should make as few changes to the existing circuits as possible. The example on page 27 of the datasheet looks this:

The modified circuit with the new ADC in our equipment looks like this:

I didn't want to change the driving op-amps because we wanted minimal changes. This is just a design, it hasn't been be sent out for manufacture, or even prototyped.

The TLE2027 op-amps are what is used in the existing product. I did a spice simulation and found that the TLE2027 nearest the ADC wasn’t able to drive a load consisting of the 5R + 470pF +5R in series without the op-amp ringing. Changing the upper resistor to 47R made the op-amp output stop ringing and ADC input settle in the minimum time (according to the spice model). The slew rate of the leftmost TLE2027 is horrible (1V/us worst case) and mostly determines the settling time of the signal at the ADC but we can live with that because our sample rate is very low (about 28us per sample). (switching time of MUX + 13.5V * / 1V per us << 28us)

However there is some advice in the datasheet page 27 that reads:

It is recommended to split the series resistance of the input filter in two equal values as shown in Figure 52. It is recommended that both input terminals see the same impedance from the external circuit.

This suggests that the circuit should be changed so that we have 27R + 470pF +27R in the filter before the ADC

But the datasheet also says that the ADC inputs are pseudo differential and that the voltage on the AINxN pin should vary by more than +/-200mV with respect to GND. If I have an 27R resistor on the on the bottom of the input filter in front of the ADC, then the AINxN pin gets a bigger transient on it that lasts for longer before settling (in the spice model). The transient on AINxN is smaller with the 5R resistor.

Also page 28 of the datasheet shows a range of different resistor values used in the input filter, but the bottom resistor is a constant 5R.

My question: which is the better selection of component values to use?

  1. 47R + 470pF + 5R ?

  2. 27R + 470pF + 27R ?

Is it OK for the AINxN pin to briefly go outside the +/-200mV range when the acquisition starts?

If the sample time is 28 us, am I worrying about the resistor values unnecessarily?

 

  • 0
    TI__Expert 5485 points

    Hi Robbie

    Ideally having symmetrical impedance on AINP and AINM should cancel the error between two input pins. So 27R / 470PF / 27R is ideal combination. If you drive AINM pin with different impedance there will be asymmetric impedance seen by AINP and AINM. This will add some error but that error will not be too high. I guess at 30ksps of sampling speed, you should get ADC performance with either RCR combination mentioned by you.

    Also if you run the ADC with clock frequency of 34MHz, that will give conversion time of around 397ns. if you can adjust CS high width, then you can maximize acquisition time. Idea here is to operate ADC at maximum possible clock frequency and CS high width. This will address settling issues caused due to higher filter resistor value at ADC input.

    When we say ADC inputs are pseudo differential that means you can have voltage of +/-200mV on AINM pin. This is typically useful when you are trying to interface signals from some other/remote source and expect to have some ground differential voltage between signal ground and ADC ground. Can you attach the spice simulation circuit and output waveform that you are seeing. I would like to check the transients you are observing on AINM pin.

    Thanks & Regards

    Abhijeet

  • 0 in reply to Abhijeet Godbole
    Prodigy 40 points

    Hi Abhijeet

    I have attached a tina schematic of the circuit. The signal that I am worried about is labelled AINxN. It has a glitch on it that occurs when the acquisition phase starts. It briefly goes to -800mV or thereabouts. This schematic has two 27R resistors for R1 and R2. If I make R1=47R and R2=5R  R2=47R and R1=5R, the glitch is still there but it is not as big.

    adc_signal_chain.tsc