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ADS1234: Reading ADS1234 - Question about clock from SPI

Uilter Witte
Intellectual 300 points
Part Number: ADS1234

Hi,

We did a design with ADS1234 to measure four load cells.

I'm using the SPI from my MCU to read the data when the pin DRDY/DOUT goes to low level.

Respecting the datasheet, on section of DATA RETRIEVEL, we set SPI speed fast enough to get a negative or positive clock of 50ns.

Using the oscilloscope we could see the 50ns of the clock signal, but when I read the data, the clock signal is not constant. The image below show the behavior of my MCU.

This behaivor of the SPI could generate a problem to the ADS1234?

The clock signal needs to be constant? The gap from each clock is 2.70us.

To read all the 24 bits, the SPI is spending @ 16.25us counting after DRDY/DOUT going to low level.
According to the datasheet, after the signal of DRDY/DOUT goes to low, I have 100ms to read all the 24bits.
My speed is set to 10SPS.

I would like to double check this behavior of my clock signal and be sure this will not be a problem for us.
Thank you!!

  • 0
    TI__Guru** 112725 points
    Hi Uilter,

    Each clock period must be 200ns or slower with the high time that must be 100ns or slower, and the low time 100ns or slower. 200ns is considered to be 50% duty cycle, which can also be considered as a maximum SCLK frequency of 5MHz. I would target a slower SCLK frequency as there is no reason that you would need to operate at the fastest possible rate when the data rate is 10sps.

    You only need to completely read the conversion result before the next conversion result is ready. So as long as your SCLK frequency is within the limits of 5MHz or less and the conversion result is read completely between conversion results you should be good. The delay time between bytes being read is not an issue.

    Best regards,
    Bob B
  • 0 in reply to Bob Benjamin
    Intellectual 300 points

    Hi Bob,

    I've understood that my clock must be faster than 100 ns, it was a big mistake on my part.
    But now is very clear after your reply, I'll decrease the spi speed.

    Thanks for clarify the behavior of the SCLK signal too.