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ADS1178 Delay Repeatability?

Judson Wilson
Intellectual 620 points
Other Parts Discussed in Thread: ADS1178, ADS1278, ADS1248

I am evaluting the  ADS1178 for a new design in a timing critical design.  The design requires repeatable timing.

I notice there are notes that cast doubt on the channel matching of the devices from part to part (but are "good" within the same part).  I also see the group delay of approx. 38 samples.

I should note that general latency is NOT critical, but repeatability of the latency IS, over the life of the product.

I plan to use the device with the frame sync protocol, with external circuitry to timestamp the frame sync signal.

Can these devices be calibrated to sub-sample timing relative to the frame sync pulse?  (i.e. can I calibrate the group delay to less than 1 / f data) ?   If not, how well could I reasonable calibrate them?

I understand an SAR would be better for this, but you would change your mind once you saw the anti aliasing filter needed for the application!

  • 0
    Intellectual 620 points

    I should note that when I say "calibrate", I will be post-processing the data after the fact, so shifting samples in time and doing other timing calculations using my calibration constants isn't an issue.

  • 0
    TI__Mastermind 43915 points

    Hi Judson,

    I do not think you are going to get what you want using the ADS1178. Let me first back up to answer your first question, you can use the ADS1278 data sheet and look at the Figures on pages 14 and 15 (specifically Figure 35) to look at the channel and part matching. I would expect the ADS1178 to have similar behavior to the ADS1278 when it comes to channel matching.

    As for the filtering, the ADS1178 uses a coefficient based FIR filter which relies on several conversions in order to give you the steep roll off performance you see in the data sheet. The latency is a factor of this incorporated filter which cannot be changed.Calibration methods are not going to be able to decrease latency. If you are fixed on using the ADS1178, you will need to put it in modulator mode and output the modulator bitstream to a FPGA and there write your own digital filter. You will probably need a Sinc based filter in order to get the settling that you want.I would recommend looking at a delta sigma that has an included Sinc filter. For example, I believe the ADS1248 has a single cycle settling time using a Sinc based filter.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Intellectual 620 points

    Tony Calabria said:
    I do not think you are going to get what you want using the ADS1178. Let me first back up to answer your first question, you can use the ADS1278 data sheet and look at the Figures on pages 14 and 15 (specifically Figure 35) to look at the channel and part matching. I would expect the ADS1178 to have similar behavior to the ADS1278 when it comes to channel matching.

    Is it saying that all parts and all channels should match within 500 pico seconds?  If that's the case, then that would be great!  I need channel matching repeatability on the order of 5-10 micro seconds.  But that's only half of the problem.

    Tony Calabria said:

    As for the filtering, the ADS1178 uses a coefficient based FIR filter which relies on several conversions in order to give you the steep roll off performance you see in the data sheet. The latency is a factor of this incorporated filter which cannot be changed.

    Great, I want repeatability, so anything that makes the latency stay fixed is a good thing!

    Tony Calabria said:
    Calibration methods are not going to be able to decrease latency.

    That is fine, I don't want to decrease latency (although it would certainly be nice).  To quote myself: "I should note that general latency is NOT critical, but repeatability of the latency IS, over the life of the product."

    My application can be thought of as "realtime with 7 milliseconds of delay", where I need to synchronize the input from the ADC to another external event, also in the past, in software.   Think of this as a datalogging application, not a controls/feedback issue.

    Anyways, I would also like to know if there is a repeatable relationship between the frame sync signal edges and the data that comes out of the serial port.  I assume that the whole operation inside is a large repeating state machine synced to the clock signal, and I am wondering if the part of the state machine that loads data into the outbound data register has any direct link to the frame sync signal.  For instance, could you say "When the frame sync signal goes low, the present value of the FIR is latched into the outbound data register on the next high-speed-system-clock low to high transition".  That would be useful, because then I could assume that this data is actually representing a signal from XXX.XX microseconds before the frame sync signal (which I am capturing with hardware), and I could use that in my calculations.

  • 0 in reply to Judson Wilson
    TI__Mastermind 43915 points

    Hi Judson,

    Thank you for the clarification. I now have a better idea what you are looking for. All the channels within one part will match within 500ps typical as they share the same internal local master clock circuitry. Channels from part to part sharing the same SPI and external master clock signal is a different story. Each part can come from a different wafer, LOT or different parts on the same wafer which is going to account for process variation causing each transistor in one ADC to another to act slightly different. For this reason, the internal local master clocks for each ADS1178 may slightly vary. Assuming the external master clock source is properly routed keeping the trace lengths the same from the source to each ADC (a tree like configuration would be best), an educated guess would be 6-10x the matching you would see on a single chip. So, maybe 5ns matching best case or maybe more (10ns+). We have not characterized this, I am just basing it off of some discussions I have had with the part's designer.

    Latency will stay fixed with the FIR filter.

    As for your Frame-Sync question - once the FSYNC rising edge appears, the output register is updated and ready to be read back. You will have to wait a minimal timing of tMSBPD and then you are able to read back all the data.

    Regards,

    Tony Calabria