We are using TI decoder-TVP5146 to convert PAL standard (625 line) with to 20-bit 4:2:2 with separate sync signals.
The image content that we are interested in is of size
640x480. But the PAL output of the TI decoder is
In the incoming PAL video, the
image that we need to capture and process (640x480) is at the center of the
Please share the register
configurations to be done in the TI decoder to capture this window of 640x480 size.
We are planning to use the
following register settings. Kindly clarify if these register settings will
ensure the desired functionality as described above.
Value that we are using
HSYNC Start Pixel Register
HSYNC Stop Pixel Register
VSYNC Start Line Register
VSYNC Stop Line Register
AVID Start Pixel Register
AVID Stop Pixel Register
VBLK Start Line Register
VBLK Stop Line Register
Are you trying capture only the center portion of a standard PAL input using standard PAL sampling?
Do you plan to use the AVID output to control capture of the active video portion? If yes, then setting up AVID Start/Stop and VBLK will define the AVID active interval.
Your VBLK settings may require tweaking. PAL is typically 576 active lines and you will need to crop to 480 active lines
Yes, I want only the center portion of the PAL input.
Yes, I am getting AVID signal as input to my FPGA.
I am using an FPGA to capture this video. Also, I need to process the video in gray scale only.
Hence, instead of BT.656, I am planning to use simple interface of 20-bit 4:2:2 mode with separate Sync signals. I will be capturing only Y component of the output.
So, shall I consider that by using AVID, VS/VBLK and HS signals, I will be able to achieve my requirement?
Also, kindly confirm if the register setting are correct?
This is Praveen. Working on some video application. I am new to this video applications. We are planning to go with Texas TVP5146M2 decoder IC and Lattice LFXP2 FPGA. and a camera interface. Can you please help me building an hardware for this application.
My mobile number: 9866339896
I am using the similar chip TVP5147 and I just want to know how do you set up the chip to output both VBLK and VS signals at the same time. The pin only allows you to output only either VS or VBLK signal.
Trident Systems Inc.
I am using a similar chip, the TVP5147M1 video decoder with a standard 720x480 NTSC input signal. My question is how do you get both VBLK and VSYNC to output at the same time since the pin on the chip only let you select either function VS or VBLK not both.
I am having to generate the VS signal manually based on VBLK and it's not working because I am always a little off as far as the exact location of the VS pulse in the frame.
I want to use tvp5146m2 input 723x579 sizer , crurent dm3730 tvp5146m2 bt565 (with embedded sync mode)input sizer 720x579,720x576 is ok.
The omap-resizer to resizer 720x576 input must be 723x579. So i need input 723x579.
Change the tvp514x-int.h
/* Number of pixels and number of lines per frame for different standards */ #define NTSC_NUM_ACTIVE_PIXELS (723) #define NTSC_NUM_ACTIVE_LINES (483) #define PAL_NUM_ACTIVE_PIXELS (723) #define PAL_NUM_ACTIVE_LINES (579)
omap3isp omap3isp: isp_wait: wait is too muchomap3isp omap3isp: ccdc 1 won't become idle!omap3isp omap3isp: omap34xx_isp_isr: sbl overflow, sbl_pcr = 00800000omap-iommu omap-iommu.0: omap2_iommu_fault_isr: da:0019b340 translation fault omap-iommu omap-iommu.0: iommu_fault_handler: da:0019b340 pgd:cf930004 *pgd:8fba9801 pte:cfba9a6c *pte:00000000omap3isp omap3isp: omap34xx_isp_isr: sbl overflow, sbl_pcr = 00800000omap-iommu omap-iommu.0: omap2_iommu_fault_isr: da:0019b340 translation fault omap-iommu omap-iommu.0: iommu_fault_handler: da:0019b340 pgd:cf930004 *pgd:8fba9801 pte:cfba9a6c *pte:00000000omap3isp omap3isp: omap34xx_isp_isr: sbl overflow, sbl_pcr = 00800000omap-iommu omap-iommu.0: omap2_iommu_fault_isr: da:0019b340 translation fault omap-iommu omap-iommu.0: iommu_fault_handler: da:0019b340 pgd:cf930004 *pgd:8fba9801 pte:cfba9a6c *pte:00000000omap3isp omap3isp: isp_wait: wait is too much
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