When we try to feed THS8200 by 4:4:4 YCbCr in VESA slave mode (1024x768) it switch to RGB input mode regardless of CSC bypass bit setting.Is it some hidden feature of the THS8200 or we missed some additional register setting ?
Pavel,
Are you trying to convert 4:4:4 YCbCr to RGB? Ouput blank levels may be changing when you switch, but color space conversion should not occur when the CSC is bypassed.
Can you send you complete register settings?
Larry,
Thanks for answer.
Yes, we try to convert 4:4:4 YCbCr to RGB888 by THS8200 but even if CSC was switched on (bypass = 0) we always got RGB signals on the screen . Because you think it should work we will make some more tests in next week and then I will send you registers, if still in troubles.
Today we again check the setup and got the results as if CSC was bypassed.We put ramps 0..255 on one data input of the THS8200 while keep another two inputs at 0.We got green,blue and red strips on the screen while we expected some green to blue and green to red in the case of CSC not bypassedbecause YCbCr 000 is green not black.Here are the registers as red back.
reg 0x0 = 0x0
reg 0x1 = 0x0
reg 0x2 = 0x4
reg 0x3 = 0x1
reg 0x4 = 0x82
reg 0x5 = 0xcb
reg 0x6 = 0x0
reg 0x7 = 0x0
reg 0x8 = 0x5
reg 0x9 = 0x7b
reg 0xa = 0x4
reg 0xb = 0x0
reg 0xc = 0x4
reg 0xd = 0x0
reg 0xe = 0x4
reg 0xf = 0x0
reg 0x10 = 0x81
reg 0x11 = 0x58
reg 0x12 = 0x6
reg 0x13 = 0xef
reg 0x14 = 0x0
reg 0x15 = 0x0
reg 0x16 = 0x21
reg 0x17 = 0x2d
reg 0x18 = 0xda
reg 0x19 = 0xbd
reg 0x1a = 0x1
reg 0x1b = 0x0
reg 0x1c = 0x0
reg 0x1d = 0x0
reg 0x1e = 0x0
reg 0x1f = 0x0
reg 0x20 = 0x0
reg 0x21 = 0x0
reg 0x22 = 0x0
reg 0x23 = 0x0
reg 0x24 = 0x0
reg 0x25 = 0x20
reg 0x26 = 0x0
reg 0x27 = 0x0
reg 0x28 = 0x0
reg 0x29 = 0x0
reg 0x2a = 0x0
reg 0x2b = 0x0
reg 0x2c = 0x0
reg 0x2d = 0x0
reg 0x2e = 0x0
reg 0x2f = 0x0
reg 0x30 = 0x0
reg 0x31 = 0x0
reg 0x32 = 0x0
reg 0x33 = 0x0
reg 0x34 = 0x5
reg 0x35 = 0x40
reg 0x36 = 0x0
reg 0x37 = 0x1
reg 0x38 = 0x87
reg 0x39 = 0x33
reg 0x3a = 0x25
reg 0x3b = 0x25
reg 0x3c = 0x0
reg 0x3d = 0x0
reg 0x3e = 0x0
reg 0x3f = 0x0
reg 0x40 = 0x0
reg 0x41 = 0x40
reg 0x42 = 0x40
reg 0x43 = 0x40
reg 0x44 = 0x53
reg 0x45 = 0x53
reg 0x46 = 0x53
reg 0x47 = 0x40
reg 0x48 = 0x40
reg 0x49 = 0x40
reg 0x4a = 0xfc
reg 0x4b = 0x44
reg 0x4c = 0xac
reg 0x4d = 0xac
reg 0x4e = 0xac
reg 0x4f = 0xff
reg 0x50 = 0x0
reg 0x51 = 0x0
reg 0x52 = 0x0
reg 0x53 = 0x0
reg 0x54 = 0x0
reg 0x55 = 0x0
reg 0x56 = 0x0
reg 0x57 = 0x0
reg 0x58 = 0x0
reg 0x59 = 0x0
reg 0x5a = 0x0
reg 0x5b = 0x0
reg 0x5c = 0x0
reg 0x5d = 0x0
reg 0x5e = 0x0
reg 0x5f = 0x0
reg 0x60 = 0x0
reg 0x61 = 0x0
reg 0x62 = 0x0
reg 0x63 = 0x0
reg 0x64 = 0x0
reg 0x65 = 0x0
reg 0x66 = 0x0
reg 0x67 = 0x0
reg 0x68 = 0x0
reg 0x69 = 0x0
reg 0x6a = 0x0
reg 0x6b = 0x0
reg 0x6c = 0x0
reg 0x6d = 0x0
reg 0x6e = 0x0
reg 0x6f = 0x0
reg 0x70 = 0x89
reg 0x71 = 0x0
reg 0x72 = 0x1
reg 0x73 = 0x6
reg 0x74 = 0x0
reg 0x75 = 0x1
reg 0x76 = 0x0
reg 0x77 = 0x7
reg 0x78 = 0xff
reg 0x79 = 0x0
reg 0x7a = 0x44
reg 0x7b = 0x0
reg 0x7c = 0x0
reg 0x7d = 0x5
reg 0x7e = 0x40
reg 0x7f = 0x53
reg 0x80 = 0x27
reg 0x81 = 0x0
reg 0x82 = 0x43
reg 0x83 = 0x0
reg 0x84 = 0x0
reg 0x85 = 0x0
reg 0x86 = 0x3e
reg 0x87 = 0x1
reg 0x88 = 0x5
reg 0x89 = 0x0
Can you try bypassing the IFIR filters in REG1Ch. It appears that you may have the 4:2:2 IFIR interpolation filter enabled while using a 4:4:4 input.