Hello,
The customer is having some issues with the TVP7002EVM kit. He using an input of 1280 x 768 @60Hz and setting the output to run @ 1080p. His video output looks redish and is constantly scrolling up. The settings he is using are:
System Initialization
(TVP7002 - Switch to EVM VGA Input)
(1280x768x60Hz- 47.8khz - 79.5MHz HS/VSin -/+)
(CSC Bypass)
for the TVP7002 Property Sheet he used the preset settings
for the THS8200 Property Sheet he is not sure what to set the HS_IN_delay and VS_IN delay to.
Thank you,
Alex
Alex,
The EVM cannot convert from a 1280 x 768 @60Hz input to 1080p output. When the 1280x768 WinVCC dataset is selected and used to program the TVP7002 and THS8200, the TVP7002 and THS8200 will both be configured for 1280x768. A scaler ICwould be required to convert between formats.
How does the customer plan to use the TVP and/or THS in their design?
I want to have as a input to the tvp2002-> VGA running @ (1280 x 720) or (1176 x 664) with a refresh rate of 60Hz
and as a output from the ths8200 I want 720p
I also want to have as a input vga (1280 x 768) @ 60Hz resolution and a output of 720p also
I wanted to have as a input (1280 x 720) VGA and have the kit convert this to 720p component video. The preset resolutions that the kit comes with does not have a setting for (1280 x 720) but is has a setting for (1280 x 768). So I downloaded the tvp7002_ths8200_evm_kit_081811.CMD file from TI and use the settings for the 720p for the THS8200 to output. Next I used the settings for 1280 x 768 for the TVP7002. I had to adjust the feed back divider so that the total pixels that were sent to the HHS8200 were under 1650 so it would fit in the 720p active window. And I got the picture to come up, I also had to uncheck the RGB out and Bypass CSC to get the proper color. So this is what I have going now
Input -> 1280 x 720 (vga) @60Hz
output -> 720p (Y Cr Cb) @60Hz
Kati,
There is 1280x720p VESA RGB format that has timing that is identical to 720p component. This format can be supported with the EVM kit using the attached CMD file. This CMD file uses a 4:2:2 embedded sync interface between the TVP7002 and THS8200. The TVP7002 converts RGB to YCbCr and the THS8200 outputs YPbPr component. Both devices are set to the 1280x720p timing.
The 1280x768 RGB format has different timing (pixel rate, line rate ) than 720p, so the output will not be true 720p.
Is there a way to do this so I have no data loss, as in use 0 - 1023 output code range and 4:4:4 format for 1280 x 720
Hi Larry Taylor
i have sum problem on the TVP7002 and DM365 card
i input from ch3 to the TVP7002 RGB 1280/702 60h
on the kernel in the tvp7002.c i add writing to TVP7002 reg
//TVP7002 set to convert RGB to YCbCr err = tvp7002_write_reg(sd,0x01,0x67); // H-PLL FEEDBACK DIVIDER MSB err = tvp7002_write_reg(sd,0x02,0x20); // H-PLL FEEDBACK DIVIDER LSB err = tvp7002_write_reg(sd,0x03,0xA0); // H-PLL CONTROL err = tvp7002_write_reg(sd,0x04,0x80); // H-PLL PHASE SELECT err = tvp7002_write_reg(sd,0x05,0x32); // CLAMP START err = tvp7002_write_reg(sd,0x06,0x20); // CLAMP WIDTH err = tvp7002_write_reg(sd,0x07,0x60); // HSOUT OUTPUT WIDTH err = tvp7002_write_reg(sd,0x08,0x00); // BLU FINE GAIN err = tvp7002_write_reg(sd,0x09,0x00); // GRN FINE GAIN err = tvp7002_write_reg(sd,0x0A,0x00); // RED FINE GAIN err = tvp7002_write_reg(sd,0x0B,0x80); // BLU FINE OFFSET err = tvp7002_write_reg(sd,0x0C,0x80); // GRN FINE OFFSET err = tvp7002_write_reg(sd,0x0D,0x80); // RED FINE OFFSET err = tvp7002_write_reg(sd,0x0E,0x20); // SYNC CONTROL 1 err = tvp7002_write_reg(sd,0x0F,0x2E); // H-PLL AND CLAMP CONTROL err = tvp7002_write_reg(sd,0x10,0x58); // SYNC ON GREEN THRESHOLD err = tvp7002_write_reg(sd,0x11,0x47); // SYNC SEPERATOR THRESHOLD err = tvp7002_write_reg(sd,0x12,0x01); // H-PLL PRE-COAST err = tvp7002_write_reg(sd,0x13,0x00); // H-PLL POST-COAST err = tvp7002_write_reg(sd,0x15,0x23); // OUTPUT FORMATTER err = tvp7002_write_reg(sd,0x16,0x11); // MISC CONTROL 1 err = tvp7002_write_reg(sd,0x17,0x00); // MISC CONTROL 2 err = tvp7002_write_reg(sd,0x18,0x11); // MISC CONTROL 3 err = tvp7002_write_reg(sd,0x19,0xAA); // INPUT MUX SELECT 1 err = tvp7002_write_reg(sd,0x1A,0x6A); // INPUT MUX SELECT 2 err = tvp7002_write_reg(sd,0x1B,0x77); // BLU AND GRN COARSE GAIN err = tvp7002_write_reg(sd,0x1C,0x07); // RED COARSE GAIN err = tvp7002_write_reg(sd,0x1D,0x00); // FINE OFFSET LSB err = tvp7002_write_reg(sd,0x1E,0x10); // BLU COARSE OFFSET err = tvp7002_write_reg(sd,0x1F,0x10); // GRN COARSE OFFSET err = tvp7002_write_reg(sd,0x20,0x10); // RED COARSE OFFSET err = tvp7002_write_reg(sd,0x21,0x08); // HSOUT OUTPUT START err = tvp7002_write_reg(sd,0x22,0x00); // MISC CONTROL 4 err = tvp7002_write_reg(sd,0x26,0x80); // AUTO LEVEL CONTROL ENABLE err = tvp7002_write_reg(sd,0x28,0x53); // AUTO LEVEL CONTROL FILTER err = tvp7002_write_reg(sd,0x29,0x08); // ADC TEST CONTROL err = tvp7002_write_reg(sd,0x2A,0x07); // FINE CLAMP CONTROL err = tvp7002_write_reg(sd,0x2B,0x00); // POWER CONTROL err = tvp7002_write_reg(sd,0x2C,0x53); // ADC SETUP err = tvp7002_write_reg(sd,0x2D,0x00); // COARSE CLAMP CONTROL err = tvp7002_write_reg(sd,0x2E,0x80); // SOG CLAMP CONTROL err = tvp7002_write_reg(sd,0x2F,0x0C); // RGB COARSE CLAMP CONTROL err = tvp7002_write_reg(sd,0x30,0x04); // SOG COARSE CLAMP CONTROL err = tvp7002_write_reg(sd,0x31,0x18); // AUTO LEVEL CONTROL PLACEMENT err = tvp7002_write_reg(sd,0x34,0x03); // MACROVISION STRIPPER WIDTH err = tvp7002_write_reg(sd,0x35,0x00); // VSYNC ALIGNMENT err = tvp7002_write_reg(sd,0x36,0x00); // SYNC BYPASS err = tvp7002_write_reg(sd,0x3D,0x06); // LINE LENGTH TOLERANCE err = tvp7002_write_reg(sd,0x3F,0x01); // VIDEO BANDWIDTH CONTROL err = tvp7002_write_reg(sd,0x40,0x47); // AVID START PIXEL LSB err = tvp7002_write_reg(sd,0x41,0x01); // AVID START PIXEL MSB err = tvp7002_write_reg(sd,0x42,0x4B); // AVID STOP PIXEL LSB err = tvp7002_write_reg(sd,0x43,0x06); // AVID STOP PIXEL MSB err = tvp7002_write_reg(sd,0x44,0x05); // VBLK START LINE OFFSET (F0) err = tvp7002_write_reg(sd,0x45,0x05); // VBLK START LINE OFFSET (F1) err = tvp7002_write_reg(sd,0x46,0x1A); // VBLK DURATION (F0) err = tvp7002_write_reg(sd,0x47,0x1A); // VBLK DURATION (F1) err = tvp7002_write_reg(sd,0x48,0x00); // F-BIT START LINE OFFSET (F0) err = tvp7002_write_reg(sd,0x49,0x00); // F-BIT START LINE OFFSET (F1) err = tvp7002_write_reg(sd,0x4A,0xE3); // 1ST CSC COEFFICIENT LSB err = tvp7002_write_reg(sd,0x4B,0x16); // 1ST CSC COEFFICIENT MSB err = tvp7002_write_reg(sd,0x4C,0x4F); // 2ND CSC COEFFICIENT LSB err = tvp7002_write_reg(sd,0x4D,0x02); // 2ND CSC COEFFICIENT MSB err = tvp7002_write_reg(sd,0x4E,0xCE); // 3RD CSC COEFFICIENT LSB err = tvp7002_write_reg(sd,0x4F,0x06); // 3RD CSC COEFFICIENT MSB err = tvp7002_write_reg(sd,0x50,0xAB); // 4TH CSC COEFFICIENT LSB err = tvp7002_write_reg(sd,0x51,0xF3); // 4TH CSC COEFFICIENT MSB err = tvp7002_write_reg(sd,0x52,0x00); // 5TH CSC COEFFICIENT LSB err = tvp7002_write_reg(sd,0x53,0x10); // 5TH CSC COEFFICIENT MSB err = tvp7002_write_reg(sd,0x54,0x55); // 6TH CSC COEFFICIENT LSB err = tvp7002_write_reg(sd,0x55,0xFC); // 6TH CSC COEFFICIENT MSB err = tvp7002_write_reg(sd,0x56,0x78); // 7TH CSC COEFFICIENT LSB err = tvp7002_write_reg(sd,0x57,0xF1); // 7TH CSC COEFFICIENT MSB err = tvp7002_write_reg(sd,0x58,0x88); // 8TH CSC COEFFICIENT LSB err = tvp7002_write_reg(sd,0x59,0xFE); // 8TH CSC COEFFICIENT MSB err = tvp7002_write_reg(sd,0x5A,0x00); // 9TH CSC COEFFICIENT LSB err = tvp7002_write_reg(sd,0x5B,0x10); // 9TH CSC COEFFICIENT MSB
i run the encoder demo .
the encoder stak and look is no buf get into .
can u send my instruction how to .
Thanks .doron sandroy
doronsa@gmail.com
Here are settings that we have used for 720p60 RGB to 20-bit 4:2:2 YCbCr with embedded syncs. This setup is for use with an external 27MHz REFCLK connected to Pin80 of the TVP7002. If this external REFCLK is not present, you will need to select internal REFCK in I2C REG1Ah. It is possible that your issue is related to the DM365 frame capture startup. Try starting or reseting frame capture after the TVP7002 has been programmed and after a 720p source has been connected.
DATASET_NAME,"TVP7002 720p60 RGB to 422 YCbCr with embedded syncs"
//TVP7002 set to convert RGB to YCbCrWR_REG,TVP7000,0x01,0x01,0x67 // H-PLL FEEDBACK DIVIDER MSB WR_REG,TVP7000,0x01,0x02,0x20 // H-PLL FEEDBACK DIVIDER LSB WR_REG,TVP7000,0x01,0x03,0xA0 // H-PLL CONTROL WR_REG,TVP7000,0x01,0x04,0x80 // H-PLL PHASE SELECT WR_REG,TVP7000,0x01,0x05,0x06 // CLAMP START WR_REG,TVP7000,0x01,0x06,0x10 // CLAMP WIDTH WR_REG,TVP7000,0x01,0x07,0x28 // HSOUT OUTPUT WIDTH WR_REG,TVP7000,0x01,0x08,0x04 // BLU FINE GAIN WR_REG,TVP7000,0x01,0x09,0x04 // GRN FINE GAIN WR_REG,TVP7000,0x01,0x0A,0x04 // RED FINE GAIN WR_REG,TVP7000,0x01,0x0B,0x90 // BLU FINE OFFSET WR_REG,TVP7000,0x01,0x0C,0x90 // GRN FINE OFFSET WR_REG,TVP7000,0x01,0x0D,0x90 // RED FINE OFFSET WR_REG,TVP7000,0x01,0x0E,0x24 // SYNC CONTROL 1 WR_REG,TVP7000,0x01,0x0F,0x2A // H-PLL AND CLAMP CONTROL WR_REG,TVP7000,0x01,0x10,0x58 // SYNC ON GREEN THRESHOLD WR_REG,TVP7000,0x01,0x11,0x40 // SYNC SEPERATOR THRESHOLD WR_REG,TVP7000,0x01,0x12,0x01 // H-PLL PRE-COAST WR_REG,TVP7000,0x01,0x13,0x00 // H-PLL POST-COAST WR_REG,TVP7000,0x01,0x15,0x43 // OUTPUT FORMATTER WR_REG,TVP7000,0x01,0x16,0x11 // MISC CONTROL 1 WR_REG,TVP7000,0x01,0x17,0x02 // MISC CONTROL 2 WR_REG,TVP7000,0x01,0x18,0x11 // MISC CONTROL 3 WR_REG,TVP7000,0x01,0x19,0xAA // INPUT MUX SELECT 1 WR_REG,TVP7000,0x01,0x1A,0xCA // INPUT MUX SELECT 2 External 27MHz REFCLK WR_REG,TVP7000,0x01,0x1B,0x77 // BLU AND GRN COARSE GAIN WR_REG,TVP7000,0x01,0x1C,0x07 // RED COARSE GAIN WR_REG,TVP7000,0x01,0x1D,0x00 // FINE OFFSET LSB WR_REG,TVP7000,0x01,0x1E,0x10 // BLU COARSE OFFSET WR_REG,TVP7000,0x01,0x1F,0x10 // GRN COARSE OFFSET WR_REG,TVP7000,0x01,0x20,0x10 // RED COARSE OFFSET WR_REG,TVP7000,0x01,0x21,0x22 // HSOUT OUTPUT START WR_REG,TVP7000,0x01,0x22,0x00 // MISC CONTROL 4 WR_REG,TVP7000,0x01,0x26,0x80 // AUTO LEVEL CONTROL ENABLE WR_REG,TVP7000,0x01,0x28,0x53 // AUTO LEVEL CONTROL FILTER WR_REG,TVP7000,0x01,0x29,0x08 // ADC TEST CONTROL WR_REG,TVP7000,0x01,0x2A,0x83 // FINE CLAMP CONTROL WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL WR_REG,TVP7000,0x01,0x2C,0x50 // ADC SETUP WR_REG,TVP7000,0x01,0x2D,0x00 // COARSE CLAMP CONTROL WR_REG,TVP7000,0x01,0x2E,0x80 // SOG CLAMP CONTROL WR_REG,TVP7000,0x01,0x2F,0x0C // RGB COARSE CLAMP CONTROL WR_REG,TVP7000,0x01,0x30,0x04 // SOG COARSE CLAMP CONTROL WR_REG,TVP7000,0x01,0x31,0x18 // AUTO LEVEL CONTROL PLACEMENTWR_REG,TVP7000,0x01,0x34,0x03 // MACROVISION STRIPPER WIDTH WR_REG,TVP7000,0x01,0x35,0x00 // VSYNC ALIGNMENT WR_REG,TVP7000,0x01,0x36,0x00 // SYNC BYPASS WR_REG,TVP7000,0x01,0x3D,0x06 // LINE LENGTH TOLERANCE WR_REG,TVP7000,0x01,0x3F,0x00 // VIDEO BANDWIDTH CONTROL WR_REG,TVP7000,0x01,0x40,0x1E // AVID START PIXEL LSB WR_REG,TVP7000,0x01,0x41,0x01 // AVID START PIXEL MSB WR_REG,TVP7000,0x01,0x42,0x22 // AVID STOP PIXEL LSB WR_REG,TVP7000,0x01,0x43,0x06 // AVID STOP PIXEL MSB WR_REG,TVP7000,0x01,0x44,0x05 // VBLK START LINE OFFSET (F0) WR_REG,TVP7000,0x01,0x45,0x05 // VBLK START LINE OFFSET (F1) WR_REG,TVP7000,0x01,0x46,0x1E // VBLK DURATION (F0) WR_REG,TVP7000,0x01,0x47,0x1E // VBLK DURATION (F1) WR_REG,TVP7000,0x01,0x48,0x00 // F-BIT START LINE OFFSET (F0)WR_REG,TVP7000,0x01,0x49,0x00 // F-BIT START LINE OFFSET (F1)WR_REG,TVP7000,0x01,0x4A,0xE3 // 1ST CSC COEFFICIENT LSB WR_REG,TVP7000,0x01,0x4B,0x16 // 1ST CSC COEFFICIENT MSB WR_REG,TVP7000,0x01,0x4C,0x4F // 2ND CSC COEFFICIENT LSB WR_REG,TVP7000,0x01,0x4D,0x02 // 2ND CSC COEFFICIENT MSB WR_REG,TVP7000,0x01,0x4E,0xCE // 3RD CSC COEFFICIENT LSB WR_REG,TVP7000,0x01,0x4F,0x06 // 3RD CSC COEFFICIENT MSB WR_REG,TVP7000,0x01,0x50,0xAB // 4TH CSC COEFFICIENT LSB WR_REG,TVP7000,0x01,0x51,0xF3 // 4TH CSC COEFFICIENT MSB WR_REG,TVP7000,0x01,0x52,0x00 // 5TH CSC COEFFICIENT LSB WR_REG,TVP7000,0x01,0x53,0x10 // 5TH CSC COEFFICIENT MSB WR_REG,TVP7000,0x01,0x54,0x55 // 6TH CSC COEFFICIENT LSB WR_REG,TVP7000,0x01,0x55,0xFC // 6TH CSC COEFFICIENT MSB WR_REG,TVP7000,0x01,0x56,0x78 // 7TH CSC COEFFICIENT LSB WR_REG,TVP7000,0x01,0x57,0xF1 // 7TH CSC COEFFICIENT MSB WR_REG,TVP7000,0x01,0x58,0x88 // 8TH CSC COEFFICIENT LSB WR_REG,TVP7000,0x01,0x59,0xFE // 8TH CSC COEFFICIENT MSB WR_REG,TVP7000,0x01,0x5A,0x00 // 9TH CSC COEFFICIENT LSB WR_REG,TVP7000,0x01,0x5B,0x10 // 9TH CSC COEFFICIENT MSB
hi Larry
Thanks to the answer .
the 720x1280p RGB is work fine.
do u have setup for :600x800P 60 RGB,1024x768P 60 RGB ,1280x1024P 60 RGB?
doron