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TVP5158: Video artifacts at temperatures below -30 degrees Celsius

Part Number: TVP5158

Hi All,

We have an issue with the TVP5158 in our custom CCA design. When the temperature dips below -30 degrees Celsius we start seeing line artifacts on the video. I've attached a couple of examples.

We've verified that the reset sequence is being followed and we are applying the 2.3.2 patch just in case. The issue has been narrowed down to the decoder by verifying the input signals look good at the pin. And the output looks good if the blue loss of sync test pattern is being applied. Only when it starts processing input video do we see the artifacts (including a blue test pattern from a generator).

The issue won't go away unless we reset the chip or power cycle the board. Even if we bring the temperature back up, the video still shows the corruption. We've also seen this on multiple boards, so we're pretty sure it's not just a one off part or PWB issue.

Along with the patch, we modify the following registers to configure the part to our use case.
TVP5158_AVD_OUT_CTRL_1, 0xB0, 0x60
TVP5158_AVD_OUT_CTRL_2, 0xB1, 0x17
TVP5158_POWER_CTRL, 0x1A, 0xF0
TVP5158_OUTPUT_FORM_CTRL_1, 0xA8, 0x04
TVP5158_OUTPUT_FORM_CTRL_2, 0xA9, 0x44
TVP5158_BLUE_SC_Y_CTRL, 0x90, 0x29
TVP5158_BLUE_SC_CB_CTRL, 0x91, 0xF0
TVP5158_BLUE_SC_CR_CTRL, 0x92, 0x6E
TVP5158_OFM_MODE_CTRL, 0xB2, 0x25

I'm hoping that only a simple register tweak is all we need to fix this!

Thanks for your help in advance!


  • In reply to Jordan Geurts:

    I don't know if the burst is normal or not unfortunately.

    I would say though that behavior or PLLs around resets can be tricky, although I would have expected the action of reset being low to disable the outputs, but from the scope captures it looks like the output is driven high whilst in reset then goes tri-state some time after the reset is de-asserted.

    Now, in general the behavior of a PLL is not stable until its reference clock source is stable and should be reset after the reference is stable. This is true for the TVP i.e. make sure the crystal is running and stable before releasing reset (which I believe you are doing), but then as you have found with your FPGA, you should not expect the FPGA PLL to behave until its reference is stable (i.e. until you have configured and enabled the TVP clock output). It could be that the FPGA PLL doesn't like the 108MHz burst (possibly triggering a 'fake' lock state) or it could be the slow droop causing metastability going in to the PLL.

    Either way, it sounds like you have found the root cause of your problems :-) This was a tough one.


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  • In reply to Steve Clynes:

    Thanks again Steve for your help. Just wanted to close up this thread with what our solution ended up being.

    We confirmed that our FPGA's PLL was trying to lock onto the TVP5158's output clock before it had stabilized. This appears to have been made worse at cold where the artifacts were first observed.

    Our fix was to reset the FPGA's PLL once the TVP5158's output clock stabilizes. This has cleared up the issue.
  • In reply to Jason Chapman16:


    Glad you have a reliable solution.



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