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"Lock status" in 5150
I have question on “lock indicator” in TVP5150 chip.
In the manual for TVP5150, document SLES043A,
On the top of page 27, there is a lock status (HVLK) register bit.
On page 36, sec. 3.22.16, register “Configuration Shared Pins”, there are also three lock indicator configuration:
What indeed are these “lock”s? What is their function? Are they related to VSYNC and HSYNC?
And for example on page 36 in the description for LOCK23
0 = FID (default, if bit 3 is selected to output FID)
1 = Lock indicator (Indicates whether device is locked both horizontally and vertically)
What does this mean? Why does the device (5150?) needs to be locked, and how it is locked?
Sincerely looking forward to answers,
Sorry for the confusion. I have attached the diagram of the Configuration Shared Pins of I2C register 03h for explanation and detail how to select lock status. Basically it is a mux to select what lock status goes to pin 23 and 24. For example, if you want to output HVLK to pin 23, you need to set bit 6 and reset bit 3 of register 0Fh and set bit 4 of register 03h. In other case, if bit 4 of register 03h and bit 3 of 0Fh are 0 then FID is output to pin 23.
Lock mean the video is locked. If HLK is 1 then video horizontal is locked and if VLK is 1 then video vertical is locked.
The TVP5150 is not recommend for new design and you should use TVP5150AM1 if you don't need scaler.
Hope it help,
Please see response for each question below:
1. Lock mean the decoder is lock to video input signal. For example, if there is no video at the input, HLK and VLK will be 0. If the is a good input, HLK and VLK are 1 then you should see a good video output. If vertical is not lock, you will see a scroll up and down picture.
2. Below is an explaination for PALI from our data sheet:
PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator:1 = Noninverted line0 = Inverted line
Yes, it is mux with HLK so you have to select from bit 4 of register 03h.
3. I don't know if it is convention or not but I use set for 1 and reset for 0. I am sorry for confusion, I will try to avoid it and use set to 0 and 1 next time.
The graphs on P16,17, and 18 show the output syncs relative to video out when in a locked state. HLK an VLK are status signals to show lock status. HLK and VLK will not change state unless there is a change in lock status. They will be at high level when locked to an inut signal and will go low if the cable is disconnected, for example. The timing of the HLK and VLK outputs is not precisely synchronized to the video output. You can also read lock status using I2C register 88h withput using the HLK and VLK status outputs. The HLK and VLK status outputs cannot be used if HSYNC and VSYNC output syncs are used, since VSYNC and HLK share the same pin. HLK and VLK status outputs are optional and not used in most designs.
When properly locked to the video input, the output syncs (VSYNC, HSYNC, and BT656 embeddedd syncs) will be properly synchronized and positioned relative to the video. If a valid NTSC(M,N) or PAL(B,G,H,N,I) video input signal is connected to the selected input channel, the TVP5150AM1 will automatically lock to the video input, if REG28h is set to the default Autoswitch mode. To automatically support formats other than these, the autoswitch mask bits in REG04h must be programmed to include the desired formats.
PAL alternates phase of the V color component every line. PALI is an indicator that the format is PAL and changes state every line when locked to a PAL source. This signal is rarely used.
When not vertically locked to the input, the VSYNC output and embedded V-bit will not be synchronized to the video input and output. When unlocked, the video that is displayed on the monitor could depend on how the video processor processes and displays the video without valid sync signals. The same video line is not repeated by the TVP5150AM1.
Thanks very much for the detailed answer. The answer on PALI resolved my doubts on this. Analog modulation is a deep subject and my knowledge on it is still very shallow.
For HLK and VLK, though I still don't have a concrete impression on what they really are, I think knowing that "HLK and VLK status outputs are optional and not used in most designs." is enough at this time.
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