Hi All,
I would like to ask a question on TVP5150 output mode:
What is the difference between:
1. 8-bit 4:2:2 YUV with discrete sync output
2. 8-bit ITU−R BT.656 interface with embedded sync output
I am confused because BT.656 also implements 4:2:2 sampling, with luminance being sampled 720 active values per line and Cb/Cr both 360 active values per line. Then
In terms of luminance and chroma sampling, is there any difference between the above two?
What is “discrete sync output”? According to BT. 656, EAV and SAV contains
F: 0 during field 1, 1 during field 2V: 0 elsewhere, 1 during field blankingH: 0 in SAV, 1 in EAV
It is therefore in this way synchronization signals are embedded. What about the “8-bit 4:2:2 YUV with discrete sync output” case? Where is its synchronization signal?
I noticed that for TVP5150, on page 5 of document SLES043A, there are
1. Pin 24: VSYNC, PALI
2. Pin 25: HSYNC
Are these two pins intended for the “discrete sync output” case?
Sincerely,
Zheng
Hi Zheng,
Yes Pin 24 and 25 are the discrete or separate sync outputs. These outputs can be activated in both 8-bit 4:2:2 YUV and 8-bit BT.656 output formats.
The only difierence between the output formats is that 8-bit BT.656 has the embedded EAV/SAV syncs, and the 8-bit 4:2:2 YUV does not. The YC video data is the same for both formats.
Dear Larry,
Thanks very much for the answer, now I understand the difference.
“These outputs can be activated in both 8-bit 4:2:2 YUV and 8-bit BT.656 output formats.”
In BT.656 mode where EAV/SAV syncs are already embedded, which could make pin 24 VSYNC and 25 HSYNC redundant, we can still choose to activate these separate sync outputs?
So in
1. Pure 4:2:2 without embedded sync, pin 24 and 25 are necessary
2. BT.656, they are redundant, and it is up to the user whether to utilize them, or just use the embedded sync signal
Is this correct?
Zheng,
Your understanding is correct, you can still activate HS/VS outputs when using BT.656, but you may not need these if the video processor uses only embedded syncs.
If the video processor uses separate syncs instead of embedded syncs, it is may be best to use 4:2:2 mode to remove the embedded syncs from the data. If the video processor does does remove the embedded syncs from active video, they could be visible at the display boundaries.
Now I understand it. Thanks very much.
Larry,
Any idea about interface of BT.656 with gstreamer.
We are using TVP BT.656 interface with FPGA(embedded synch). FPGA in turn transmits the data to a processor through PCIe for encoding on gstreamer.
Very litttle literature is available on BT.656 interface with gstreamer. Thanks in adance.