I'm using THS8200, but can't set registers to get colorbar output at 640x480. My frequence of CLKIN is 27MHz.
Please give me a correct reg settings.
Thanks in advance!
The internal color bar genration is limited to graphics formats having positive syncs. Below is a setup for SVGA60Hz based on a 27MHz input clock. To output the correct line rate and sync width, the line length, HS width, and color bar width must be adjusted based on the actual input clock and specified pixel rate for a particular format. VGA60Hz has negative sync polarities, so it cannot be supported.
DATASET_NAME,"SVGA60Hz 800x600x60 40MPPS, Internal Color Bar using 27MHz CLKIN"
// A 27MHz clock must be supplied to CLKIN
WR_REG,THS8200,0x01,0x03,0xA3 // chip_ctl VESA Color Bars enabled, Master mode WR_REG,THS8200,0x01,0x19,0xBD // csc_offset3 WR_REG,THS8200,0x01,0x2A,0x93 // dtg_spec_e color bar start WR_REG,THS8200,0x01,0x34,0x02 // dtg_total_pixel_msb 1056 x 27 / 40WR_REG,THS8200,0x01,0x35,0xc9 // dtg_total_pixel_lsb WR_REG,THS8200,0x01,0x36,0x00 // dtg_linecnt_msb WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb WR_REG,THS8200,0x01,0x38,0x86 // dtg_mode VESA Mode WR_REG,THS8200,0x01,0x39,0x22 // dtg_frame_field_msb total lines/frame = 628WR_REG,THS8200,0x01,0x3A,0x74 // dtg_frame_size_lsb WR_REG,THS8200,0x01,0x3B,0x74 // dtg_field_size_lsb WR_REG,THS8200,0x01,0x3C,0x43 // dtg_vesa_cbar_size (800x27/40) /8
WR_REG,THS8200,0x01,0x70,0x56 // dtg_hlength_lsb HSOUT width=128 pixels x 27/40 WR_REG,THS8200,0x01,0x71,0x00 // dtg_hdly_msb WR_REG,THS8200,0x01,0x72,0x01 // dtg_hdly_lsb WR_REG,THS8200,0x01,0x73,0x07 // dtg_vlength_lsb WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb WR_REG,THS8200,0x01,0x77,0x05 // dtg_vdly2_msb WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb WR_REG,THS8200,0x01,0x7A,0x01 // dtg_hs_in_dly_lsb WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb WR_REG,THS8200,0x01,0x7C,0x01 // dtg_vs_in_dly_lsb WR_REG,THS8200,0x01,0x82,0x5f // pol_cntl +HS+VS ouputs
In reply to Larry Taylor:
Thank you very much, I have got test output now.
I followed your settings, but i can't got the color bars output to my computer monitor. My platform is based on 6446EVM, and using the EVM's lsp. Now I doubt whether the VPBE had wrong settings(e.g. VENC) . Can you give some adives?
Thanks in advance!
In reply to Paul Tron:
You reported ealier that you were able to display the VGA60Hz test bars using a 27MHz clock. Are you using the same setup with 6446EVM? Have you confirmed that the EVM is ouputting the same 27MHz clock? If a differnet clock frequncy is being used, the THS8200 settings need to be adjusted to compensate for clock frequency change.
I got it ! Thanks a lot.
I had got another problem. My colorbar can't display in PC monitor or projector, but it can display in other monitor which integrated PC mode、HDMI and video mode. The colorbar can display in the PC mode in this monitor.I'm sure the Vsync and Hsync is right. You said 'VGA60Hz has negative sync polarities, so it cannot be supported.',what does it mean? My board just used one THS8200 without THS7303 and CDCE949, i don't what goes wrong. Can you give me some advices?
Any help would be appreciated.
Design Engineer --China
Correct, the THS8200 has issues with negative output sync polarities, when using internal color bar generation. Can you set up for an SVGA fomat which uses positive sync polarities? If you need to support only VGA with negative syncs, you can set up for postive syncs and then use invertors.
Always check the THS8200 output syncs with a scope for correct timing. Some monitors may not be compatible with 3.3V syncs. 3.3V/5V level translators are recommended on the output syncs to drive the monitor.
I have another question.There is a QT application, could i display it on my monitor via VGA .
We will need more detail on the QT applcation to answer this.
I got it.My UI and video could display on my monitor via VGA.But there is another problem.My Hsync and Vsync amplitude just about 1.8V.Some PC monitor can't get the H/Vsync signals. I think there was something wrong with my circuits.In ths8200 document i found there were three pins named VDD_IO(NO. 19, 46, 70),and was described that 'I/O ring power, 1.8 V or 3.3 V nominal'.In my board,VDD_IO pins connected 1.8V.I think these pins can effect H/Vsync signals output. If i want H/Vsync pins output 3.3V signals should i have give VDD_IO pins 3.3V. Any help would be appreciated.
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