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Chengping,

What DM365 > THS8200 platform are you uing?

By 16-bit RGB input format, do you mean the 16-bit RGB 4:4:4 as shown in Figure 4-3 of the THS8200 datasheet?  The THS8200 input bit assignment for the RGB 4:4:4 format is different from that of 20-bit 4:2:2.

If a 16/20-bit 4:2:2 RGB format is being used, instead of the 16-bit RGB 4:4:4,  then you will need to use the color space converter in the THS8200 to convert from the 4:2:2 YCbCr format to RGB out. 

Larry,

Thanks for your reply.

My board is designed by myself, it is based both on DM365EVM and THS8200 Daughter-Card.

My 16-bit RGB format is 4:4:4 shown in Figure 4-3.

When I change input format of THS8200 to 20-bit(only 16-bit used) 4:2:2 YCbCr, I also change output format of DM365 and add CSC settings in THS8200. I don't know lost some settings. Do you have any tips?

In table 4-1 of the THS8200 datasheet, In cross INPUT INTERFACE 20-BIT and [PRESET] VESA, no a 'X' is showed. Do you know, if THS8200 can set to both generate VESA signal(for computer monitor) and input a 20-bit 4:2:2 YCbCr data with DEDICATED TIMING?

Thanks in advance!

Larry,

Thank you very much!  I have success to implement VESA output.

I want to know how to set the dm365 output yuv422 data .  my project is the same with your ， i use dm365 +ths8200+ths7303 output VGA 720p 。

I can get the 720p VGA video now ，  but I found the color is wrong ， like this ！

what wrong with me？ please help me 。 thank you！

If you are trying to display VGA RGB from a YUV (YCbCr) input, you will need to use the color space convertere in the THS8200 to convert to RGB.  See the CSC setting below for YCbCr>RGB conversion.

DATASET_NAME," YCbCr to RGB Using HDTV CSC coefficients and CSM for Output Scaling "
//                                  //CSC setup for YCbCr to RGB Conversion.  HDTV CSC coefficients used  

                                                 SA ,  Data

WR_REG,THS8200,0x01,0x04,0x81 // csc_ric1           
WR_REG,THS8200,0x01,0x05,0xD5 // csc_rfc1           
WR_REG,THS8200,0x01,0x06,0x00 // csc_ric2           
WR_REG,THS8200,0x01,0x07,0x00 // csc_rfc2           
WR_REG,THS8200,0x01,0x08,0x06 // csc_ric3           
WR_REG,THS8200,0x01,0x09,0x29 // csc_rfc3           
WR_REG,THS8200,0x01,0x0A,0x04 // csc_gic1           
WR_REG,THS8200,0x01,0x0B,0x00 // csc_gfc1           
WR_REG,THS8200,0x01,0x0C,0x04 // csc_gic2           
WR_REG,THS8200,0x01,0x0D,0x00 // csc_gfc2           
WR_REG,THS8200,0x01,0x0E,0x04 // csc_gic3           
WR_REG,THS8200,0x01,0x0F,0x00 // csc_gfc3           
WR_REG,THS8200,0x01,0x10,0x80 // csc_bic1           
WR_REG,THS8200,0x01,0x11,0xBB // csc_bfc1           
WR_REG,THS8200,0x01,0x12,0x07 // csc_bic2           
WR_REG,THS8200,0x01,0x13,0x42 // csc_bfc2           
WR_REG,THS8200,0x01,0x14,0x00 // csc_bic3           
WR_REG,THS8200,0x01,0x15,0x00 // csc_bfc3           
WR_REG,THS8200,0x01,0x16,0x14 // csc_offset1        
WR_REG,THS8200,0x01,0x17,0xAE // csc_offset12       
WR_REG,THS8200,0x01,0x18,0x8B // csc_offset23       
WR_REG,THS8200,0x01,0x19,0x15 // csc_offset3        

//Map 64-940 RGB code range to 0-1023 full-scale range       
WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low    
WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low   
WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low   
WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high   
WR_REG,THS8200,0x01,0x45,0x53 // csm_clip_bcb_high  
WR_REG,THS8200,0x01,0x46,0x53 // csm_clip_rcr_high  
WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy       
WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb      
WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr      
WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb    
WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
WR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb    
WR_REG,THS8200,0x01,0x4D,0xAC // csm_mult_bcb_lsb   
WR_REG,THS8200,0x01,0x4E,0xAC // csm_mult_rcr_lsb   
WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode    

thanks for your reply.

I have already set the csc and csm, my ths8200 setting is

  WR_REG,THS8200,0x01,0x03,0x01 // chip_ctl  frequency range=high

  //YCbR to RGB         
  WR_REG,THS8200,0x01,0x04,0x81 // csc_ric1           
  WR_REG,THS8200,0x01,0x05,0xD5 // csc_rfc1           
  WR_REG,THS8200,0x01,0x06,0x00 // csc_ric2           
  WR_REG,THS8200,0x01,0x07,0x00 // csc_rfc2           
  WR_REG,THS8200,0x01,0x08,0x06 // csc_ric3           
  WR_REG,THS8200,0x01,0x09,0x29 // csc_rfc3           
  WR_REG,THS8200,0x01,0x0A,0x04 // csc_gic1           
  WR_REG,THS8200,0x01,0x0B,0x00 // csc_gfc1           
  WR_REG,THS8200,0x01,0x0C,0x04 // csc_gic2           
  WR_REG,THS8200,0x01,0x0D,0x00 // csc_gfc2           
  WR_REG,THS8200,0x01,0x0E,0x04 // csc_gic3           
  WR_REG,THS8200,0x01,0x0F,0x00 // csc_gfc3           
  WR_REG,THS8200,0x01,0x10,0x80 // csc_bic1           
  WR_REG,THS8200,0x01,0x11,0xBB // csc_bfc1           
  WR_REG,THS8200,0x01,0x12,0x07 // csc_bic2           
  WR_REG,THS8200,0x01,0x13,0x42 // csc_bfc2           
  WR_REG,THS8200,0x01,0x14,0x00 // csc_bic3           
  WR_REG,THS8200,0x01,0x15,0x00 // csc_bfc3           
  WR_REG,THS8200,0x01,0x16,0x14 // csc_offset1        
  WR_REG,THS8200,0x01,0x17,0xAE // csc_offset12       
  WR_REG,THS8200,0x01,0x18,0x8B // csc_offset23       
  WR_REG,THS8200,0x01,0x19,0x15 // csc_offset3  

  WR_REG,THS8200,0x01,0x1C,0x53 // dman_cntl  20bit 422

  WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1        
  WR_REG,THS8200,0x01,0x1E,0x00 // dtg_y_sync2        
  WR_REG,THS8200,0x01,0x1F,0x00 // dtg_y_sync3        
  WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1     
  WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2     
  WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3     
  WR_REG,THS8200,0x01,0x23,0x2A // dtg_y_sync_upper   
  WR_REG,THS8200,0x01,0x24,0x2A // dtg_cbcr_sync_upper
  
  WR_REG,THS8200,0x01,0x34,0x06 // dtg_total_pixel_msb adjust for various graphics formats
  WR_REG,THS8200,0x01,0x35,0x72 // dtg_total_pixel_lsb
  WR_REG,THS8200,0x01,0x36,0x80 // dtg_linecnt_msb    
  WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb    

  WR_REG,THS8200,0x01,0x38,0x87 // dtg_mode     VESA Slave       

  WR_REG,THS8200,0x01,0x39,0x27 // dtg_frame_field_msb  adjust for various graphics formats
  WR_REG,THS8200,0x01,0x3A,0xEE // dtg_frame_size_lsb 
  WR_REG,THS8200,0x01,0x3B,0xFF // dtg_field_size_lsb 
  //CSM setup to map YCbCr to FS RGB        
  WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low    
  WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low   
  WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low   
  WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high   
  WR_REG,THS8200,0x01,0x45,0x53 // csm_clip_bcb_high  
  WR_REG,THS8200,0x01,0x46,0x53 // csm_clip_rcr_high  
  WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy       
  WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb      
  WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr      
  WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb    
  WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
  WR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb    
  WR_REG,THS8200,0x01,0x4D,0xAC // csm_mult_bcb_lsb   
  WR_REG,THS8200,0x01,0x4E,0xAC // csm_mult_rcr_lsb   
  WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode   
         
  WR_REG,THS8200,0x01,0x70,0x28 // dtg_hlength_lsb    adjust HSOUT width for various formats
  WR_REG,THS8200,0x01,0x71,0x01 // dtg_hdly_msb       
  WR_REG,THS8200,0x01,0x72,0x4 // dtg_hdly_lsb       
  WR_REG,THS8200,0x01,0x73,0x05 // dtg_vlength_lsb     adjust VSOUT width for various formats
  WR_REG,THS8200,0x01,0x74,0x02 // dtg_vdly_msb       
  WR_REG,THS8200,0x01,0x75,0xED // dtg_vdly_lsb       
  WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb   
  WR_REG,THS8200,0x01,0x77,0x07 // dtg_vdly2_msb      
  WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb      
  WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb   adjust for horizontal alignment
  WR_REG,THS8200,0x01,0x7A,0x0A // dtg_hs_in_dly_lsb  
  WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb   adjust for horizontal alignment
  WR_REG,THS8200,0x01,0x7A,0x32 // dtg_hs_in_dly_lsb  
  WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb   adjust for vertical alignment
  WR_REG,THS8200,0x01,0x7C,0x00 // dtg_vs_in_dly_lsb  
  WR_REG,THS8200,0x01,0x82,0x5B // pol_cntl   HS/VSin ++, HS/VSout++, FID -  
  WR_REG,THS8200,0x01,0x03,0x00
  mdelay(50);
  WR_REG,THS8200,0x01,0x03,0x01

also when display white picture , the G channel wave picture is

but the R and B channel wave picture is

I think if the THS8200 is programed in the "RGB output with Sync signal inserted on G channel" mode?

I want to know how to program   THS8200  in the "RGB output without Sync signal  insertion/General-Purpose Application DAC" mode?

please help me!

Can you double check the REG 0x38 setting after the THS8200 is set up?  Sync insertion is disabled when the THS8200 is in VESA slave mode.  When your settings are used here, a sync tip is not present on the G output. 

Is it  possible that your settings are not being written to the THS8200, or that they are being over written by system software?

WR_REG,THS8200,0x01,0x38,0x87 // dtg_mode     VESA Slave       

thanks for your reply !

I have read out the REG 0x38 after write in 0x87;

 err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_MODE, 0x87);          //WR_REG,THS8200,0x01,0x38,0x87 // dtg_mode     VESA Slave

.....

printk ("DTG1_MODE=%x\n",i2c_smbus_read_byte_data(ths8200_client, THS8200_DTG1_MODE));

printk vale is "0X87", that is mean 0X87 has been written to the THS8200 .

now I know that about 350mv insert the  G channel  is not the Sync signal but the blank level ! I want to know how can I set the black level in blanking !

I have tried to  set the blank REG to 0x00 ,

WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1        
  WR_REG,THS8200,0x01,0x1E,0x00 // dtg_y_sync2        
  WR_REG,THS8200,0x01,0x1F,0x00 // dtg_y_sync3        
  WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1     
  WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2     
  WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3     
  WR_REG,THS8200,0x01,0x23,0x00 // dtg_y_sync_upper   
  WR_REG,THS8200,0x01,0x24,0x00 // dtg_cbcr_sync_upper

but that is still have 350mv in the G channel. 

but if I set the REG to :

WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1        
  WR_REG,THS8200,0x01,0x1E,0x00 // dtg_y_sync2        
  WR_REG,THS8200,0x01,0x1F,0x00 // dtg_y_sync3        
  WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1     
  WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2     
  WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3     
  WR_REG,THS8200,0x01,0x23,0x2A // dtg_y_sync_upper   
  WR_REG,THS8200,0x01,0x24,0x2A // dtg_cbcr_sync_upper

The  waveform is changed to R,G,B three channel all have 500mv blank level !  

I am crazy !!!   what is wrong ?? how can I set the black level (R,G,B three channel are all 0 mv)  in blanking ??

Do you have a DE signal that can be connected to the THS8200 FID pin? 

See the dtg2_fid_de_cntl description in REG 82h for using DE to force a blank level in VESA slave mode.

thank you very much!

connect the DE singal to the FID pin ,then set the blank level REG

  WR_REG,THS8200,0x01,0x1E,0x00 // dtg_y_sync2        
  WR_REG,THS8200,0x01,0x1F,0x00 // dtg_y_sync3        
  WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1     
  WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2     
  WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3     
  WR_REG,THS8200,0x01,0x23,0x00 // dtg_y_sync_upper   
  WR_REG,THS8200,0x01,0x24,0x23 // dtg_cbcr_sync_upper   

then I can get the black blank level , and the color is right !

set the 0x24 REG to 0x23 is very important ! If I set to 0x00 then the  350mv will be inserted in the G channel.  I don't konw why?

thank you !

Please note that I have no clue how the folks on this thread got to the point of configuring the THS8200, without also fixing up the VPIF driver and clock.  This must use some other platform, and some other _____ whatever.

If you're searching for how to about VGA from a DM6467 based on the EVM, then here's how I did it: