Video Converters - Forum - Recent Threads

THS8200EP - Register setting for 1080P50/60 20bit 4:2:2

Kawai — Wed, 15 May 2013 16:25:56 GMT

Hi.

Please tell us how to set the Register address 0x03 bit[7:6] for 1080p50/60 20bit 4:2:2, 148.5MHz.

SLEC026A shows the recommended register settings and I see this file programs Address 0x03 = 0x01.

In the datasheet, I see that if CLK_IN > 80MHz, DLL should be bypassed to disable 2x frequency generation.

Doesn't this mean that for CLK_IN=148.5MHz, Address 0x03 bit6 and/or bit7 is set ?

Please tell us why the recommended register setting is Address 0x03=0x01 and how it operates internally.

Our customer is having trouble on waveform and picture when using address 0x03=0x01, but is solved when address 0x03=0x81.

TVP5150AM1 PAL-M color lock

John Whittington1 — Tue, 14 May 2013 06:49:39 GMT

In our application, we want to decode a PAL-M signal with the TVP5150AM1.

When we force standard register 0x28 to 0x06, there is no color,
and no color subcarrier lock in status register 0x88 bit 3.

TVP5150AM1 ROM code patch V04.8C.AA did not seem to help.

My TVP5158 hardware can decode the PAL-M signal with color.

Can you confirm that PAL-M is supported on TVP5150AM1?

Regards,

John Whittington

TVP7002 detect video standard

Steven Weng1 — Thu, 16 May 2013 07:23:26 GMT

Hello All,

I use TVP7002 register - clocks per line(39h-3Ah) and lines per frame(37h-38h) to detect what video standard have been capture. And set the related parameters of TVP7002 registers.

It's ok for most of VESA video standard!

But in 1280x768@60 and 1366x768@60, it cant distinguish.

clocks per line: 136

lines per frame: 798

It almost the same.

How can I distinguish?

BTW, I am capturing the VGA source(RGB, VESA standard) and output the 20bit 4:2:2 format embedded sync.

Thanks!!

Regards,

Steven

THS8200-EP - I2C line voltage at VDD_IO=1.8V

Kawai — Fri, 17 May 2013 11:11:15 GMT

Hi Team,

Could you please tell me if I2C (SDA and SCL) is 3.3V tolerant when VDD_IO=1.8V ?

Is the Absolute Maximum Ratings for SDA/SCL is -0.5V to VDD_IO+0.5V ?

---

Our customer is using THS8200-EP at VDD_IO=1.8V, I2C bus pull-up voltage at 3.1V. It seems it is out of range.

Best Regards,

Kawai

THS8200 - DAC output amplitude control

Kawai — Wed, 15 May 2013 16:45:03 GMT

Hi.

Could you please tell me how to control the DAC output amplitude level ?

Changing address 0x4A to 0x4E, amplitude changed but sync level did not change.

To control all the signal level at once(blanking, sync, active video ), which address shold we control ?

Is it address 0x16 to 0x19, csc_offset1/2/3 ?

Best Regards,

Kawai

How to solve the "video noise" with the TVP7002?

SuitJune Young — Sun, 12 May 2013 11:59:37 GMT

Hello,We use TVP7002 to capture HD PC graphcs video from NoteBook or other video sources.

Now,the video we get has some video noises.It is a "lighting point" with RED or GREEN color.

What may cause this LIGHTING POINT?How to solve it?

Expecting for any reply.

Thanks in advance.

duplicate DVI SIGNAL

dominique rachel — Wed, 15 May 2013 09:49:38 GMT

We have need to duplicate the DVI signal for test.

Have you a solution 1input DVI to 2 output DVI ?

Best regards

dominique RACHEL

internal registers of the TVP7002

Michael Rivlin — Fri, 10 May 2013 09:38:39 GMT

There are some ready-only registers In the TVP7002 which indicate resolution parameters: lines for frame (37h-38h), Hsyn width (3Bh), etc.

How can I convert , for example, data of register 3Bh to real width of Hsyn? For example, my input VGA has resolution DMT1660. For this resolution width of Hsyn is 1.185uS, or 192 (or C0h) pixels per Hsyn. But in the register "3Bh" I read the following data: 20 03 06 04 00 FA 01 3A. What relationship between 192 and this data?

Note. I use EVM THS8135 which use 27MHz oscillator for the TVP7002.

TVP5158 - rolling strips of missing lines in superframe.

Alexey Smirnov — Thu, 18 Oct 2012 12:02:37 GMT

Hi,

I'm working with video captured from TVP5158.

My data flow is following:

TVP5158->DM368->Linux kernel->MCVIP TVP5158 SW Driver->Resizer(just to change chroma format)->h264 Encoder->Some video customers...

There are many issues in drivers, code of that not so good :)

But the main issue is that in superframe which was delivered from TVP5158 - there ae missing lines (8-10 lines per every camera).

Could you please help me with fix of the issue.

TVP5158 patch is letest.

Couple of pictures below, there are D1 mode, four cameras, odd end enev lines separated, all half-frames from all cameras are combined to one frame.

Even halfs at the top, odd, at the bottom.

First picture - TVP5158 - without any patches:

Second picture - with latest patch 2.03.02:

Ready to hear any uideas how to remove missing lines.

Possible trying to play with some TVP registers?

Regards,

Alexey.

VGA converter

xiaohua zheng — Fri, 19 Apr 2013 01:19:46 GMT

Hello,

I want to find a VGA receiver chip which can support VGA interface,and translate VGA format to RGB(24bits,30bits or 36bits) parallel signals to my FPGA. The highest resolution of incoming video maybe 1600*1200@60(fpixel=162MHz) and 1080p60(fpixel=148.5MHz). one chip VS one channel is what I want.

Would you please give me some suggestions?

DVI to LVDS

John Iest — Wed, 08 May 2013 21:10:24 GMT

I'm designing a circuit that requires DVI to LVDS conversion. I reviewed you application note SLLA325A and it looks like I would use two chips. TFP401A and SN75LVDS83B. I need to convert 1024 x 768 to LVDS. No scaling required. We'll these chips do the job. I need to know ASAP because I need to start my design.

John Iest

Amest Corporation

Replacement of TVP5150 by TVP5151 - issues

Claus Maehringer — Thu, 02 May 2013 14:43:38 GMT

Dear all,

currently I am trying to replace a design using the TVP5150PBS (TQFP 32) by an equivalent TVP5151,
as the TVP5150 was set to NRND recently. The datasheet of the TVP5151 states on page 25:

"TVP5151 is pin compatible with TVP5150/A/AM1, and the following differences should be considered
when an upgrade is planned.
• IO_DVDD supply can be any voltage from 1.8 V to 3.3 V.
• AVID/CLK_IN is input during RESETB. If this input is used as the clock source, XTAL1/OSC pin must
be grounded."

So, regarding Hardware the case is quite clear (beside the beforementioned points the clock frequency
on the TVP5151 is now 27MHz instead of 14.318MHz), but there are some small differences in the register set:
Especially the contrast control reg. (0x0C) on the TVP5151 is marked to be "reserved".
Our application software writes contrast values settings from the user to this register.
The circuit worked so far, also varying the contrast is functional, but according to the spec
this shouldn't be done.

My questions:
1. Is it safe to still write values to this register, although it is marked as "reserved"?
2. What is the risk if I do so, what could happen?
3. Any other registers to better keep untouched on the TCP5151 that were used on the TVP5150?
4. How is contrast control be done without having a distinct register on the TVP5151?
5. Are there any other known issues, when replacing an TVP5150 with an 5151?

Thanx in advance
Bye
Claus

tvp5151 issue

Sarra Benguerga — Fri, 03 May 2013 15:31:38 GMT

Hello all,

We are using a tvp5151 connected to a CVBS signal generator (PAL).

Vsync/Hsync/DV/CLK signals are behaving properly at tvp5151 I/O pads and there are some activities on its YOUT pads.

However, we fail to obtain a decoded image. The display contains only "flashes". These flashes are random and not always present.

Any help is really appreciated.

Best regards,

Sarra

THS8200 resizing feature( to convert image size)?

Devin Park — Fri, 03 May 2013 08:55:15 GMT

Hi,

I wonder it THS8200 can convert image size.

For example, 1080P -> 320x240. Is it possible?

At past, it seemed to be simmlar post at E2E but now I can't find the article.

Thanks and BR,

Devin

Interface with the LMH0030

Felix Villar — Sun, 28 Apr 2013 00:36:20 GMT

Hello,

What analog video encoder can be directly interfaced with the LMH0030 serializer? The main purpose is to create a composite (SD) / components (HD) to SD/HD-SDI device.

Additionally, do you have an audio ADC to achieve the ancillary data required for the LMH0030?

Thanks,

Félix.

TVP5154A Impedance

Mike McNally — Thu, 25 Apr 2013 23:57:26 GMT

I am student working on a project using the TVP5154A. I am working on the board layout and due to my limited budget I do not have the money for a controlled impedance PCB. There is not much in the data sheet about the NTSC video input impedance and YCbCr 4:2:2 output impedance. I am assuming the NTSC component input requires 75 ohms impedance trace, am I correct?

Also does the YCbCr require a specified impedance? How strict are these impedances since they are not called out in the data sheet? Do you have any tips to achieve the required impedances on these line(s)?

Thanks

how to detect resolution of input video for TVP7002?

Michael Rivlin — Tue, 23 Apr 2013 10:55:43 GMT

The TVP7002 must be configured via I2C for specific resolution of input VGA (or component) video. Thinking about application as stand-alone VGA-2-DVI converter for multiformat (DMT, CVT, SDTV, HDTV) VESA sources, how the video resolution can be detected? Is it enough to measure frequency and polarity of Hsyn and Vsyn ?

Thanks in advance

TVP5158

Max Parker — Wed, 24 Apr 2013 11:17:18 GMT

Hello,,,
I just hope i am not going against the rules of this site.
I am young engineer after college. i want to use TVP5158 in my project.

first question is: what can i do with audio pins (pins in, out and selection) , if i don't use audio part ? connect them to ground through resistors or leave them open?
second question: if i use only one video output (DVO_A_[7:0]) what to do with other outputs? connect them to ground through resistors or leave them open?

Thanks very much

TVP5147M1 produces wrong field order for NTSC

Alex Pollard — Tue, 23 Apr 2013 00:44:05 GMT

We are using an e-CAMNT_MX53x video capture board which incorporates a TVP5147M1. The e-CAMNT_MX53x is made by e-consystems. It plugs into a i.MX53 Quick Start Board. The datastream between the decoder and processor is BT.656

When we capture NTSC video using the capture board straight out of the box, with the demo micro SD card provided by e-consystems (linux), following the instructions in their Test Report, but selecting option 5 so that both fields are displayed, we find the fields are out of order.

I note that it looks OK when the image is slowly rolling before synchronisation,

but not when it has ceased rolling:

You can see the black lines in the graphical elements generated by the NTSC camcorder and at the top and bottom of the picture, this is indicative of the fields being out of order. Due to the blurriness of the compressed video it isn't immediately apparent in the image itself, but it is there. This problem also occurs with NTSC signals from other devices.

I think it is related to analog PAL being "upper field first" and NTSC being "lower field first". It is as if the field order is set for PAL not NTSC.

We have this same problem in our modified version of the drivers - it is a low-level issue with the e-CAMNT_MX53x board. We have also seen it on another e-CAMNT_MX53x board, so it is a general problem.

I suspect there is either some problem with the way e-consystems have designed the board, or their driver does not adjust the field order correctly for NTSC.

I had a look at the datatsheet

http://www.ti.com/lit/ds/symlink/tvp5147m1.pdf

and have tried changing a couple of registers related to Field IDentification (FID) in the e-consystems-provided driver tvp5147m1_tvin.ko:

tvp5147m1_write_reg(REG_SYNC_CONTROL, 0x10);

to change the polarity of the FID (Field ID?)

and

tvp5147m1_write_reg(REG_FID_CONTROL, 0x01 );

where I’ve defined

#define REG_FID_CONTROL (0x57)

I have tried each of the above together and alone (with the other defaulted), and nothing has changed the field order problem with NTSC.

Has anyone experienced the same problem or have suggestions?

TVP5158 4-Ch D1 Super-Frame Format

Ravindra — Wed, 17 Apr 2013 11:10:35 GMT

Hello,

In our current product based on DM8148 and TVP5158, we are planning to utilize the TVP5158 in Line-Interleaved 4-Channel D1 format.

We need information on the format of the Super-frame that will be constructed by the TVP5158.

I understand that the for 8-BIT 656 4-Ch Super-Frame, the TVP5158 will insert the EAV, followed by Horz Blanking+SAV+Start Code+Channel Data.

Is there a pictorial representation of how the one frame is completely merged together?

Also, in terms of the total frame size I am assuming that the Super-frame size will be

4+248+4+8+One Channel Line-Data [720 * 32bits]+4 = 3148 bytes

The same repeated 4 times for 4 different channels i.e., 480 *4 = 1920

Is the above calculation right?

Thanks,
Ravindra

TVP7002 and 1080p 24/25/30

Aran Gallagher — Thu, 10 Sep 2009 06:00:34 GMT

Hi,

I would like to add component video support for 1080p24 /25 /30 to my system using the TVP7002, however the datasheet(page 12) states that is does not support v.freq rates less than 40Hz ....

Ive tried setting the PLL etc in the hope that it is possible regardless of the datasheet... but no luck so far (it just doesnt lock properly) .... does anyone have any suggestions of how to implement support for these lower frame rates using the 7002?

Thanks, Aran.

TVP7002

Igor Gorelik — Mon, 02 Jan 2012 11:37:13 GMT

Hello,

Pls see the email from my customer below and advise.

Thx.

Igor

We are working on the TVP7002 together with DM368 ,RGB input, unfortunately the drivers for the TVP7002 does not include the option for RGB input, but we succeeded to capture 1280X720. so h/w works, but each resolution/Hz to set-up TVP7002 is pain in the .... do you have tool or code that configure the the TVP7002

to the following resolutions:

SVGA 800 X 600 ,50 Hz

XGA 1024 X 768, 50 Hz

WXGA 1360 X 768 , 50 Hz

about TVP5158's function and sample code

Yusuke Nomoto — Wed, 17 Apr 2013 12:47:41 GMT

Hello,

I have two questions for TVP5158.

1. Can I operate the video decoder function and audio ADC function in parallel?
I think that it is possible, because each function is separated in Functional Block Diagram.

2. Is there sample code for TVP5158 with linux?
I found the "mcvip_tvp5158_v010013_20100211.zip" at "http://e2e.ti.com/support/data_converters/videoconverters/f/376/t/41768.aspx".
Is this sample code for TVP5158 with linux?

Thanks

Nomoto

Where is the TVP5158EVM's J9 connector?

Yusuke Nomoto — Mon, 15 Apr 2013 11:06:24 GMT

Hi,

I have a question for TVP5158EVM.
I'm checking "Figure 1. TVP5158 EVM Block Diagram" in SLEU108 (User's Guide),
however I can't find the J9 connector.
I think that "Digital Video Out To Davinci HD EVM" corresponds to J9.
Is this correct?

Thanks

Nomoto

about TVP5158 problem

yunge feng — Mon, 24 Sep 2012 23:07:29 GMT

Hi, all,

about TVP5158 problem, I hope you help me analyze and better proposals for our system design, thank you very much!

System descriptions or requirements:

My design is required to achieve 4 channel independent SD CVBS input, TVP5158 conversion into 4 independent BT656 data, respectively, to the 4 independent H.264 coding chip, by The encoded TS data and then time division multiplexed output.

special attention

1, TVP5158 input 4 channels of independent CVBS signal, are different from the signal source is provided, such as: channel 1/2 provided by STB, channel 3/4 provided by DVD. I want to express Mean, input to the TVP5158 4 channel CVBS analog signal, the field line is not synchronized to together.

2, after the treatment by TVP5158 BT656 data, request is 4 channel independent output. The four channel BT656 data will be sent to 4 independent H.264 code chip, the output of the TVP5158 CLK_P ( 27MHz ) clock will be sent to 4 independent H.264 coding chip.

Now I encountered problems:

1, when TVP5158 did not download firmware, 4 output BT656 data in the final H.264 encoded output image having upper and lower rolling line.(Please check the attachment of TS stream file)

2, when the download of firmware, firmware version is: v020302, 4 output BT656 data in the final H.264 encoded output image, only the PORT A in normal, other channel PORT B/C/D all is not normal.

I now doubt:

1, my design is correct, or whether it can achieve.

2, I think, the TVP5158 can't use, because it only from PORT A output data, so now only the output of PORT A BT656 data of normal, other PORT B/C/D are not normal.

3, if in my system must use the TVP5158, need to change the output model of the TVP5158, CLK_P output 108MHz clock, put 4 road BT656 multiplexed together from

PORT A output, again from the back end with FPGA processing, data separation, output of four independent BT656 data and clock, and then sent to the H.264 coding chip.

In addition, in this system, I used 4 pieces of TVP5146 instead of TVP5158, did not appear above all the problems.

Very much looking forward to your reply, thank you!

Yunge