We are using TVP51246M2 Digital Video Decoder in one of our projects to display frames of size 640x480. We are considering VBLK on VS pin and AVID, FID signals as control signals to read the data from Decoder chip. We have set the VBLK configuration register to generate 240 rows in each field and AVID configuration register to generate valid signal for 640 pixels.
We get the image of size 640x480 properly, but the locking of sync(VBLK and AVID) signals is not proper.
Will decoder give the image boundaries like this way or Is there any other configuration to be done to get proper image output always.
Thanks & Regards,
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