I am converting RGB to YCbCr using the Color Space Conversion block in the THS8200. In the data manual as an example a coefficient set is given for RGB to HDTV YCbCr conversion. Now my question is why I got a wrong image used the same coefficient set for RGB to HDTV YCbCr conversion in the data manual. Is there some thing worng with register settings?
Following are my settings:
WR_REG,THS8200,0x01,0x1c,0x30// input: 24bit YCbCr/RGB 4:4:4 ;the 2 LSBs for each channel are connected to ground.
WR_REG,THS8200,0x01,0x38,0x82// output: 720P YCbCr
WR_REG,THS8200,0x01,0x82,0x0F// Timing of video input bus is derived from HS, VS, and FID dedicated inputs.
WR_REG,THS8200,0x01,0x04,0x00 // csc_ric1 WR_REG,THS8200,0x01,0x05,0xda // csc_rfc1 WR_REG,THS8200,0x01,0x06,0x80 // csc_ric2 WR_REG,THS8200,0x01,0x07,0x78 // csc_rfc2 WR_REG,THS8200,0x01,0x08,0x02 // csc_ric3 WR_REG,THS8200,0x01,0x09,0x0c // csc_rfc3 WR_REG,THS8200,0x01,0x0A,0x02 // csc_gic1 WR_REG,THS8200,0x01,0x0B,0xdc // csc_gfc1 WR_REG,THS8200,0x01,0x0C,0x81 // csc_gic2 WR_REG,THS8200,0x01,0x0D,0x94 // csc_gfc2 WR_REG,THS8200,0x01,0x0E,0x81 // csc_gic3 WR_REG,THS8200,0x01,0x0F,0xdc // csc_gfc3 WR_REG,THS8200,0x01,0x10,0x00 // csc_bic1 WR_REG,THS8200,0x01,0x11,0x4a // csc_bfc1 WR_REG,THS8200,0x01,0x12,0x02 // csc_bic2 WR_REG,THS8200,0x01,0x13,0x0c// csc_bfc2 WR_REG,THS8200,0x01,0x14,0x80 // csc_bic3 WR_REG,THS8200,0x01,0x15,0x30 // csc_bfc3 WR_REG,THS8200,0x01,0x16,0x00 // csc_offset1 WR_REG,THS8200,0x01,0x17,0x08 // csc_offset12 WR_REG,THS8200,0x01,0x18,0x02 // csc_offset23 WR_REG,THS8200,0x01,0x19,0x00 // csc_offset3
//CSM settings to map 64-940 RGB code range to 0-1023 full-scale range WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high WR_REG,THS8200,0x01,0x45,0x3F // csm_clip_bcb_high WR_REG,THS8200,0x01,0x46,0x3F // csm_clip_rcr_high WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msbWR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb WR_REG,THS8200,0x01,0x4D,0x91 // csm_mult_bcb_lsb WR_REG,THS8200,0x01,0x4E,0x91 // csm_mult_rcr_lsb WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode
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