• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 47 subscribers
  • Views 537 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TVP7002 Pixel Clock Settings and Jitter

Adrian Soltero
Intellectual 1135 points
Other Parts Discussed in Thread: TVP7002

Hi,

 

A customer I am working with has been having a problem with the clock output.  They are working with 720p video which the datasheet recommends using a pixel rate of 74.25 MHz and the medium VCO range.  They had an improvement in performance of the clock when they changed the VCO setting to low. Is there any issue for using this configuration for production?

Also, the clock output has 7 nsec of jitter which is much greater than the spec of 500 psec of jitter.  Any idea as to what is causing it or how to improve it?

 

Thanks,

Adrian

 

  • 0
    TI__Genius 16810 points

    Adrian,

    They may have a noisy PLL supply.  Adding filtering on this could help.  The stability and quality of the 720p input source will also contribute to the jitter.  Have they tried using different 720p sources to see if it is source dependent.

    The VCO settings in the datasheet are our recommeded settings based on PLL tests that were run.

    Larry

  • 0 in reply to Larry Taylor
    Expert 1150 points

    Larry,


    I am having a jitter issue on the TVP7002. I can see some vertical bars for some resolutions.

    I looked with an oscilloscope the signals, and it is clear that there is a jitter on the PLL that creates 2 harmonics.

    Instead of being at let's say 75Mhz, I would have 2 frequencies around the 75Mhz. We can see them by doing a FFT.

    Those 2 frequencies create some regular vertical bars. It looks like the PLL jitter might be the cause.

    Do we need to adjust the PLL filter (on FILT1 and FILT2 pins)  based on the resolutions? Is there any documentation of the selection of the PLL filter?

    Thx

    Karim