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TVP5158: 4Ch Line interleave mode clocking query

Roma Bhagat1
Prodigy 110 points
Other Parts Discussed in Thread: TVP5158

Hello,

We are using TVP5158 and interfacing it with Davinci processor.

Problem statement:
- We are using TVP5158 in 4-Ch line interleaved mode, and it is mentioned in datasheet, that output clock OCLK_P is synchronised with all 4 output ports. On page 96 of datasheet, it is given Video output clock and data timing table, propagation delay from falling edge of OCLK_P/ OCLK_N.

Our queries are:
1) Can in 4-Ch line interleaved mode, output clock can either be OCLK_N or OCLK_P, w.r.t. which data is delayed?
2) If OCLK_N is possible for 4-ch line interleaved mode, then the propagation delay for data remains same 0.22ns- 1.5ns w.r.t rising edge or falling edge?
3) If only OCLK_P is to be used for 4-ch line interleave mode, then we would like to know if it is possible to invert the clock?
4) Page 76 of datasheet, shows, output clock polarity can be inverted. Does that mean, OCLK_P can give be inverted for 4-ch line interleaved mode and will the propagation delay remain same?

Pls confirm on this at the earliest.

Thanks & Regards,
Roma Bhagat

  • 0
    TI__Mastermind 43875 points

    Roma,

    #1) In 2 channel mode _P and _N are simple the inversions of each other. This allows the receiving system to use the same data buss for both streams, but use only one clock signal. In this mode each receiver only 'sees' one of the data streams since it is only capturing data on one of the clock pulses. The receiver should use either the positive going or the negative going clock depending on what the active clock edge is that it requires.

    #2) For 4 channel mode use OCLK_P.

    #3) See register OFM Mode control (offset B2h) bit 4.

    #4) Yes, all clock polarity control does is invert the clock. Timings remain the same with respect to the ACTIVE edge.

    BR,

    Steve