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TVP 5158 register allocation

Other Parts Discussed in Thread: TVP5158, TVP5154

Hi,

I want to use TVP5158 to process data from camera, I use C6678 to write reg through I2C,
Now I just collect 1-ch D1, and the values written to reg are similar to default values in
datasheet, but then I find that there is no clock 27M out from OCLK_P(OCLK_P is enabled),

and the crystal oscillator does work, the value read from 0x00 and 0x01 is 0x00,

Is this problem result from registers allocation or hardware?

Thanks.

  • Is anything at all working? Do you have the single channel use case working?

    Is the pixel clock output active? Are the data out pins active? Please check these with an oscilloscope.

    The 27MHz oscillator output should be active by default so either the device is not receiving a good crystal input, the device is in reset, the output has been turned off through software or there is a hardware issue holding the oscillator pin inactive.

    Reading I2C registers should not return 0x00. This implies that something is holding the I2C SDA lines incorrectly. Can you please check the I2C lines with an oscilloscope to make sure that they are toggling correctly?

    BR,

    Steve

  • Hi Steve,

    I have checked the input oscillator ,I2c and other related pins, they did work correctly. And I found that after I write a reg, the value read form it was not same some time, but the problem said above still exist. 

    What tests should I do now?

    Thank you for reply.

  • Also I found that the values read from 0x05 and 0x06 is 0x00,

    so I tried to download patch on 5158, refer to the "TVP5158 Patch Code Download Guidelines “, this is my steps on C6678:

    ///step 1
    ucBuffer[0] = 0xFE;
    ucBuffer[1] = 0x0F;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ///step 2
    ucBuffer[0] = 0xE0;
    ucBuffer[1] = 0x01;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);

    ucBuffer[0] = 0xE8;
    ucBuffer[1] = 0x60;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ucBuffer[0] = 0xE9;
    ucBuffer[1] = 0x00;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ucBuffer[0] = 0xEA;
    ucBuffer[1] = 0xB0;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);

    ///step 3
    ucBuffer[0] = 0xFE;
    ucBuffer[1] = 0x0F;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ///step 4
    ucBuffer[0] = 0xE8;
    ucBuffer[1] = 0x00;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ucBuffer[0] = 0xE9;
    ucBuffer[1] = 0x00;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ucBuffer[0] = 0xEA;
    ucBuffer[1] = 0x40;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ///step 5
    ucBuffer[0] = 0xE1;
    I2C_write(addrI2C, 1 ,ucBuffer,I2C_WAIT);
    I2C_write(addrI2C, 5716,patchv1,I2C_WAIT);////?
    ///step 6
    ucBuffer[0] = 0xE0;
    ucBuffer[1] = 0x03;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);

    ucBuffer[0] = 0xE8;
    ucBuffer[1] = 0x60;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ucBuffer[0] = 0xE9;
    ucBuffer[1] = 0x00;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ucBuffer[0] = 0xEA;
    ucBuffer[1] = 0xB0;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ///step 7
    ucBuffer[0] = 0xE0;
    ucBuffer[1] = 0x02;//0x00
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);

    ucBuffer[0] = 0xE8;
    ucBuffer[1] = 0x60;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ucBuffer[0] = 0xE9;
    ucBuffer[1] = 0x00;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);
    ucBuffer[0] = 0xEA;
    ucBuffer[1] = 0xB0;
    I2C_write(addrI2C, 2,ucBuffer,I2C_WAIT);

    Is my steps wrong? Will this operation make difference to my problem?

    Thanks!

  • If you do not read back the correct value after writing then you have an issue with your I2C reliability.

    You need to debug the quality of your I2C.

    Make sure that the rise and fall times of the signals are good and clean.

    Make sure your master checks the ACK state to make sure transactions are correct.

    For each write do multiple reads to try to determine if this is a write problem or a read problem or both.

    Make sure there are no other I2C masters which might be corrupting the signal.

    Make sure you are leaving enough time after device reset before starting I2C transactions.

    Try slowing down the I2C clock rate.

    Make sure the I2C voltage levels are correct.

    Make sure there isn't any noise on the I2C lines.

    You seem to have an I2C integrity issue.

    BR,

    Steve

  • Don't bother with patch code until you are 100% that I2C is working correctly.

    BR,

    Steve

  • I think the I2C is working correctly, because there is a SAA7115 on I2C, and no problems occur when I write and read  it in same way.

    Thanks

  • The only things it can be are...

    1) Bad power supplies
    2) Bad oscillator/clock
    3) Bad reset
    4) Bad I2C

    Just because your other device works does not mean that there are not any reflections or other signal integrity issue affecting the TVP5154.

    Please check the things I mentioned previously.

    BR,

    Steve

  • Hi Steve,

    I have tested the aspects you mentioned, nearly all of them work correctly.

    The reset signal is referred to the datasheet,

    So what else should I test now?

    Thanks.

  • What do you mean by "nearly all" are correct?

    Can you check that all the power supply pins ON THE TVP are correct?

    As I mentioned previously the clock output should be active immediately after reset has finished so if it isn't then there is not really much that can be wrong.


    Power, reset, crystal are the only possibilities.

    Try forcing the reset signal again after the system is stable, then check the oscillator output to make sure it oscillates.

    BR,

    Steve

  • Hi Steve,

    Are you sure that the clock output can be active immediately after reset has finished? I referred to the datasheet and found that the reg "OFM MODE CONTROL" whose subaddress is 0xB2, it has a bit "Out_Clk_ P_En", is this bit related to the clock out?

    If the bit dose not influnce the output clock, I am confused because power, reset, crystal all work correctly.

    Thanks.

  • Fan,

    Sorry for the confusion...

    Yes, you are correct, the pixel clock is not enabled by default. I was thinking about the oscillator output, which is bit 5 of register B2h.

    Please measure the oscillator output to make sure that it is oscillating.

    BR,

    Steve

  • Hi Steve,

    I have measured the osc_out and found a stable 27M clock output. Did it prove that the TVP5158 work correctly?

    As to the value read from regs did not match the write value, someone said that it may related to the number of bits written on I2C one time, my way to write regs was as follow,

    addrI2C = 0xB0>1;

    for(i =0; i<133; i++)
    {
           ucBuffer[0]= tvp5158PAL[i].regsubaddr;
           ucBuffer[1]= tvp5158PAL[i].regvule;
           I2C_write(addrI2C,
                              2,
                              ucBuffer,
                              I2C_WAIT);
    }

    8078.Keystone_I2C_init_drv.c
    /*  ============================================================================
     *   Copyright (c) Texas Instruments Inc 2012
     *
     *   Use of this software is controlled by the terms and conditions found in the
     *   license agreement under which this software has been supplied.
     *   ===========================================================================
     */
    /** ============================================================================
     example for I2C initialization and read/write driver on Keystone DSP
     * =============================================================================
     *  Revision History
     *  ===============
     *  Jan 9, 2012 Brighton  file created
     * =============================================================================*/
    
    #include <stdio.h>
    #include <string.h>
    #include "Keystone_common.h"
    #include "Keystone_I2C_init_drv.h"
    
    CSL_I2cRegs * i2cRegs = (CSL_I2cRegs *)CSL_I2C_DATA_CONTROL_REGS;
    
    /*I2C output clock <= 400 KHz*/
    Uint32 I2C_speed_KHz= 400;
    
    /*Initialize I2C as master*/
    void I2C_Master_Init(Uint32 i2c_speed_KHz)
    {
    	if(i2c_speed_KHz>400)
    	{
    		puts("ERROR: I2C speed can not be higher than 400KHz!");
    		return;
    	}
    
    	I2C_speed_KHz= i2c_speed_KHz;
    
    	/*I2C internal input clock is (DSP core clock)/6,
    	it should be Prescale to 7~12MHz for I2C internal working clock*/
    	i2cRegs->ICPSC= (CPU_CLK_KHZ/6/I2C_MODULE_FREQ_KHZ)-1;
    
    	/*I2C output clock <= 400 KHz*/
    	i2cRegs->ICCLKL= (I2C_MODULE_FREQ_KHZ/I2C_speed_KHz)/2-6;
    	i2cRegs->ICCLKH= (I2C_MODULE_FREQ_KHZ/I2C_speed_KHz)/2-6;
    
    	/*Master mode. The I2C is a master and generates the serial clock on the SCL pin.*/
    	i2cRegs->ICMDR= i2cRegs->ICMDR|
    		(1<<CSL_I2C_ICMDR_MST_SHIFT)|
    		(1<<CSL_I2C_ICMDR_FREE_SHIFT);
    
    	/*Take I2C controller out of reset: 
    	enable I2C controller (set IRS bit = 1 in ICMDR).*/
    	i2cRegs->ICMDR= i2cRegs->ICMDR|
    		(1<<CSL_I2C_ICMDR_IRS_SHIFT);
    
    	TSC_init(); 	//enable TSC for timeout count
    	
    }
    
    /*I2C read/write operations can not re-enter, so before any I2C operation, 
    this function should be called to block other I2C operations*/
    void I2C_block()
    {
    	; 	//to be done
    }
    
    /*after complete an I2C operation, free I2C for other operations*/
    void I2C_free()
    {
    	; 	//to be done
    }
    
    /*wait a flag in ICSTR, 
    retun 1 when the ICSTR&flag_mask=expect, return 0 when timeout*/
    Int32 I2C_wait_flag(Uint32 flag_mask, Uint32 expect)
    {
    	Uint32 preTSC;
    	Uint32 delay;
    	Uint32 theoryCycleForOneByte;
    	volatile Uint32 flag;
    
    	preTSC= TSCL;
    	theoryCycleForOneByte= (CPU_CLK_KHZ/I2C_speed_KHz)*9;
    
    	flag= i2cRegs->ICSTR&flag_mask;
    
    	/*Wait until I2C flag= expect value*/
    	while(flag!= expect)
    	{
    		/*if wait time is much larger than theoretical transfer time of
    		a byte, then it is looked as timeout.*/		
    		delay= TSC_count_cycle_from(preTSC);
    		if(delay> 100*theoryCycleForOneByte)
    		{
    			printf("I2C_wait_flag 0x%x timeout at device 0x%x, ICSTR=0x%x\n", 
    				flag_mask, i2cRegs->ICSAR, i2cRegs->ICSTR);
    
    			/*reset and reinitialize I2C when timeout happens*/
    			i2cRegs->ICMDR= 0;
    			I2C_Master_Init(I2C_speed_KHz);
    
    			return 0;
    		}
    		flag= i2cRegs->ICSTR&flag_mask;
    
    	};
    
    	return 1;
    }
    
    /*read "uiByteCount" data from I2C device with "slaveAddress",
    data save in buffer pointed by "ucBuffer".
    if "wait", polling until data trasfer complete, otherwise, let interrupt
    handle the data.
    return number of bytes received.*/
    Uint32 I2C_read(Uint32 slaveAddress, Uint32 uiByteCount, 
    	Uint8 * ucBuffer, I2C_Wait wait)
    {
    	int i;
    
    	/*I2C read/write operations can not re-enter, so before any I2C operation, 
    	this function should be called to block other I2C operations*/
    	I2C_block();
    	
    	/*Place I2C in reset (clear IRS = 0 in ICMDR)*/
    	i2cRegs->ICMDR= 0;
    	
    	/*Configure I2C as Master (MST = 1)
    	Data Receiver (TRX = 0)*/
    	i2cRegs->ICMDR= 
    		(1<<CSL_I2C_ICMDR_FREE_SHIFT)|
    		(1<<CSL_I2C_ICMDR_MST_SHIFT);
    		
    	i2cRegs->ICCNT= uiByteCount;
    	i2cRegs->ICSAR= slaveAddress;
    
    	/*Make sure the interrupt status register (ICSTR) is cleared*/
    	/*Read ICSTR and write it back (write 1 to clear) ICSTR = ICSTR*/
    	i2cRegs->ICSTR= i2cRegs->ICSTR;
    	/*Read ICIVR until it is zero*/
    	while(i2cRegs->ICIVR);
    
    	/*Take I2C controller out of reset: enable I2C controller (set IRS bit = 1 in ICMDR).*/
    	i2cRegs->ICMDR= i2cRegs->ICMDR| 
    		(1<<CSL_I2C_ICMDR_IRS_SHIFT);
    
    	/*Wait until bus busy bit is cleared (BB = 0 in ICSTR).*/
    	if(0==I2C_wait_flag(CSL_I2C_ICSTR_BB_MASK, 0))
    	{
    		/*after complete an I2C operation, free I2C for other operations*/
    		I2C_free(); 
    		return 0;
    	}	
    	/*Generate a START event(set STT = 1 in ICMDR).*/
    	/*End transfer/release bus when transfer is done. 
    	Generate a STOP event (set STP = 1 in ICMDR).*/
    	i2cRegs->ICMDR= i2cRegs->ICMDR| 
    		(1<<CSL_I2C_ICMDR_STT_SHIFT)|
    		(1<<CSL_I2C_ICMDR_STP_SHIFT);
    
    	if(I2C_NOWAIT==wait)
    	{
    		/*exits after programmation of the control registers,
    		interrupt service routine should be used to handle the data.*/
    		return 0;
    	}
    
    	for(i= 0; i< uiByteCount; i++)
    	{
    		
    		/*Wait until data is received (ICRRDY = 1 in ICSTR).*/
    		if(0==I2C_wait_flag(CSL_I2C_ICSTR_ICRRDY_MASK, CSL_I2C_ICSTR_ICRRDY_MASK))
    		{
    			/*after complete an I2C operation, free I2C for other operations*/
    			I2C_free();
    			return 0;
    		}	
    		
    		/*read data from ICDRR.*/
    		ucBuffer[i]=i2cRegs->ICDRR;
    	}
    
    	/*Wait until bus busy bit is cleared (BB = 0 in ICSTR).*/
    	if(0==I2C_wait_flag(CSL_I2C_ICSTR_BB_MASK, 0))
    		uiByteCount= 0;
    
    	/*after complete an I2C operation, free I2C for other operations*/
    	I2C_free(); 
    
    	return uiByteCount;
    }
    
    /*transfer "uiByteCount" data from "ucBuffer" to I2C device with address
    "slaveAddress". if "wait", polling until data trasfer complete, otherwise, 
    let interrupt handle the data.
    return number of bytes transfered.*/
    Uint32 I2C_write(Uint32 slaveAddress, Uint32 uiByteCount, 
    	Uint8 * ucBuffer, I2C_Wait wait)
    {
    	int i;
    
    	/*I2C read/write operations can not re-enter, so before any I2C operation, 
    	this function should be called to block other I2C operations*/
    	I2C_block();
    	
    	/*Place I2C in reset (clear IRS = 0 in ICMDR)*/
    	i2cRegs->ICMDR= 0;
    	
    	/*Configure I2C as Master (MST = 1)
    	Data Receiver (TRX = 0)*/
    	i2cRegs->ICMDR= 
    		(1<<CSL_I2C_ICMDR_FREE_SHIFT)|
    		(1<<CSL_I2C_ICMDR_TRX_SHIFT)|
    		(1<<CSL_I2C_ICMDR_MST_SHIFT);
    		
    	i2cRegs->ICCNT= uiByteCount;
    	i2cRegs->ICSAR= slaveAddress;
    
    	/*Make sure the interrupt status register (ICSTR) is cleared*/
    	/*Read ICSTR and write it back (write 1 to clear) ICSTR = ICSTR*/
    	i2cRegs->ICSTR= i2cRegs->ICSTR;
    	/*Read ICIVR until it is zero*/
    	while(i2cRegs->ICIVR);
    
    	/*Take I2C controller out of reset: enable I2C controller (set IRS bit = 1 in ICMDR).*/
    	i2cRegs->ICMDR= i2cRegs->ICMDR| 
    		(1<<CSL_I2C_ICMDR_IRS_SHIFT);
    
    	/*Wait until bus busy bit is cleared (BB = 0 in ICSTR).*/
    	if(0==I2C_wait_flag(CSL_I2C_ICSTR_BB_MASK, 0))
    	{
    		/*after complete an I2C operation, free I2C for other operations*/
    		I2C_free(); 	
    		return 0;
    	}	
    	
    	/*Generate a START event(set STT = 1 in ICMDR).*/
    	/*End transfer/release bus when transfer is done. 
    	Generate a STOP event (set STP = 1 in ICMDR).*/
    	i2cRegs->ICMDR= i2cRegs->ICMDR| 
    		(1<<CSL_I2C_ICMDR_STT_SHIFT)|
    		(1<<CSL_I2C_ICMDR_STP_SHIFT);
    
    	if(I2C_NOWAIT==wait)
    	{
    		/*exits after programmation of the control registers,
    		interrupt service routine should be used to handle the data.*/
    		return 0;
    	}
    
    	for(i= 0; i< uiByteCount; i++)
    	{
    		/*Wait until transmit is ready (ICXRDY = 1 in ICSTR).*/
    		if(0==I2C_wait_flag(CSL_I2C_ICSTR_ICXRDY_MASK, CSL_I2C_ICSTR_ICXRDY_MASK))
    		{
    			/*after complete an I2C operation, free I2C for other operations*/
    			I2C_free(); 
    			return 0;
    		}	
    		
    		/*transmit data to ICDXR.*/
    		i2cRegs->ICDXR= ucBuffer[i];
    	}
    
    	/*Wait until bus busy bit is cleared (BB = 0 in ICSTR).*/
    	if(0==I2C_wait_flag(CSL_I2C_ICSTR_BB_MASK, 0))
    		uiByteCount= 0;
    
    	/*after complete an I2C operation, free I2C for other operations*/
    	I2C_free(); 
    	
    	return uiByteCount;
    }
    
    

    Was there any problem in my codes?

    Thanks.

  • The oscillator does not prove anything other than the oscillator is working and the TVP is not in reset. It is, however, critical that the oscillator is running correctly before any I2C transactions occur.

    Next, do not write to reserved registers. Your code seems to write to all registers in the range 0 to 133 but there are many reserved registers in this range.

    Finally, have you tried adding a significant delay after each read or write? Some transactions can take time to process and your software should really monitor the SCL signal to make sure it behaves correctly when clock stretching is required. As a test try adding a 5ms delay after each write or read to make sure you are not sending transactions without the required delays.

    BR,

    Steve

  • I have added a 5ms delay after each write operation, but there is no difference.

    The attached file is my reg allocation.

    Then, I found that the value dismatched now was limited to 0xe0,0xe1,0xe8 these three regs.

    Thank you for more suggestion.

    3107.tvp5158h.c
    #include "tvp5158h.h"
    
    //5158 default
    
    TVP5158_ConfParams tvp5158PAL[] = {
    	{0x0D,0x02},{0x0E,0xEF},/*{0x0E,0x03}*/{0x0F,0x03},{0x10,0x80},{0x11,0x80},{0x12,0x00},
    	{0x13,0x80},{0x14,0x80},{0x16,0x10},{0x18,0x40},{0x19,0x00},{0x1A,0x00},
    	{0x1B,0x00},{0x1C,0x0C},
    	{0x24,0x00},{0x25,0xF5},{0x26,0x00},{0x27,0x00},{0x29,0x06},{0x2A,0x1E},
    	{0x2B,0x04},{0x2C,0x00},{0x2D,0xF2},{0x2E,0x08},
    	{0x34,0x6A},{0x35,0x08},
    	{0x48,0x7A},/*{0x48,0x84}*/{0x49,0x00},{0x4A,0xD0},{0x4B,0x02},
    	{0x5C,0x28},{0x5D,0x09},{0x5E,0x30},{0x5F,0x03},{0x60,0x00},{0x61,0x09},
    	{0x7C,0x02},{0x7D,0x08},
    	/*{0x7E,0x03},{0x7F,0x03},{0x80,0x03},*/
    	{0x81,0x00},{0x85,0x03},{0x87,0x00},{0x88,0x03},{0x89,0x16},{0x8C,0x00},
    	{0x8F,0x04},{0x90,0x10},{0x91,0x80},{0x92,0x80},{0x93,0x00},{0x96,0x60},
    	{0x97,0x50},{0x9E,0x0A},{0x9F,0xBC},{0xA0,0xBC},{0xA8,0x44},{0xA9,0x40},
    	{0xAD,0x00},{0xAE,0x01},{0xAF,0x00},{0xB0,0x00},{0xB1,0x90},{0xB2,0x25},//{0xB2,0x24},{0xB2,0x26},
    	{0xB3,0xE4},{0xB4,0xE4},{0xB5,0x00},{0xB6,0x1B},{0xB7,0x04},{0xB8,0x40},
    	{0xB9,0x00},{0xBA,0x00},
    	/*{0xBB,0x00},{0xBC,0x00},{0xBD,0x00},{0xBE,0x00},{0xBF,0x00},*/
    	{0xC0,0x00},{0xC1,0x88},{0xC2,0x88},{0xC3,0xC9},{0xC4,0x01},{0xC5,0x00},
    	{0xC6,0x00},{0xC7,0x00},{0xC8,0x00},
    	/*{0xC9,0xA5},{0xCA,0xFF},{0xCB,0x7E},{0xCC,0x01},*/
    	{0xE0,0x00},{0xE1,0x00},{0xE8,0x00},{0xE9,0x00},{0xEA,0x00},{0xF4,0x00},
    	{0xF6,0x00},{0xFE,0x0F},{0xFF,0x01}
    };
    
    TVP5158_ConfParams tvp5158TEST[] = {
    	{0x0D,0x02},{0x0E,0xEF},{0x0F,0x00},{0x10,0x80},{0x11,0x80},{0x12,0x00},
    	{0x13,0x80},{0x14,0x00},{0x16,0x50},{0x18,0x40},{0x19,0x00},{0x1A,0x00},
    	{0x1B,0x10},{0x1C,0x0D},
    	{0x24,0x01},/*���ܵ���20,94��A2�޷����Ĵ���*/{0x25,0xF5},{0x26,0x00},{0x27,0x00},{0x29,0x06},{0x2A,0x1E},
    	{0x2B,0x04},{0x2C,0x00},{0x2D,0xF2},{0x2E,0x08},
    	{0x34,0x6A},{0x35,0x08},
    	{0x48,0x7A},/*{0x48,0x84}*/{0x49,0x00},{0x4A,0xD0},{0x4B,0x02},
    	{0x5C,0x28},{0x5D,0x1B},{0x5E,0x30},{0x5F,0x03},{0x60,0xB0},{0x61,0x09},
    	{0x7C,0x02},{0x7D,0x08},
    	/**/{0x7E,0x03},{0x7F,0x03},{0x80,0x03},
    	{0x81,0x00},{0x85,0x03},{0x87,0x00},{0x88,0x00},{0x89,0x98},{0x8C,0x00},
    	{0x8F,0x04},{0x90,0x10},{0x91,0x80},{0x92,0x80},{0x93,0x00},{0x96,0x60},
    	{0x97,0x50},{0x9E,0x0A},{0x9F,0xBC},{0xA0,0xBC},{0xA8,0x44},{0xA9,0x40},
    	{0xAD,0x00},{0xAE,0x01},{0xAF,0x00},{0xB0,0x00},{0xB1,0xD7},{0xB2,0x27},
    	{0xB3,0xE4},{0xB4,0xE4},{0xB5,0x00},{0xB6,0x1B},{0xB7,0x04},{0xB8,0x40},
    	{0xB9,0x00},{0xBA,0x00},
    	/**/{0xBB,0x00},{0xBC,0x00},{0xBD,0x00},{0xBE,0x00},{0xBF,0x00},
    	{0xC0,0x00},{0xC1,0x88},{0xC2,0x88},{0xC3,0xC9},{0xC4,0x01},{0xC5,0x00},
    	{0xC6,0x00},{0xC7,0x00},{0xC8,0x00},
    	/**/{0xC9,0xA5},{0xCA,0xFF},{0xCB,0x7E},{0xCC,0x01},
    	{0xE0,0x00},{0xE1,0x00},{0xE8,0x00},{0xE9,0x00},{0xEA,0x00},{0xF4,0x3F},//{0xF4,0x00},
    	{0xF6,0x00},{0xFE,0x0F},{0xFF,0x01}
    };
    

  • You cannot randomly access the VBUS registers like this. Do not access registers which you do not intend to access.

    Do not write to reserved registers. This is clearly stated in the datasheet, section 4.1

    E0/E1/E8 are special registers for accessing the internal processor bus and their values are not expected to be necessarily the same as those values written.

    Please only read/write the registers which you actually need to change/monitor.

    Given that these are the only registers which are now 'incorrect' I think we have found your issue. Please ensure first that the I2C clock rate is less than 400KHz. Next, either make sure you monitor SCL and implement clock stretching or include a delay after each transaction which is long enough to accomodate and clock stretching which might be occurring.

    BR,

    Steve

  • First, I am sorry that I make a mistake because "only e0/e1/e8 are incorrect" is not always the truth. Other regs may go wrong sometime, include 0xb2.

    Then, I have modified the code, the I2C clock (400K/300K/200K), adding delay(5ms/10ms/50ms), and remove write operation to reserved registers, but these did not work.

    As to your suggestion" Do not access registers which you do not intend to access.", I have no idea how to do with that because I do not know which regs are necessary.

    Thanks.

  • If you don't know what registers you need to modify, then you probably don't need to modify it !!!

    The registers are not simply static so you may not always read back what you have written.

    In order to get the device fully functioning in its default and automatic mode then the only registers you need to set are the clock and data output enables and the source select.

    You simply can't randomly write/read registers without understanding what they do.

    BR,

    Steve

  • Now I just write values from regs 0xB0 to 0xB7 and 0xC3, also I rdownload patch tvp5158_patch_v02_01_14 and make it run. However, I still can not find OCLK_P output clock and data output.

    I have checked the signal input and clock input, they are all right.

    So what else should I do now?

    Thanks!

  • Try using one of the datasets from the file attached here. Use the dataset which corresponds to the setup you are trying to get working, although for an initial test to check the clock and outputs it really doesn't matter which set you try. Don't worry about the THS or ADI parts of these files. They are only needed for the EVM.

    Do not worry about loading firmware for the moment. Get the basics working first. Firmware patch updates only address specific issues or changes and they may not be relevant to you.

    5756.tvp5158_041213.zip

    BR,

    Steve

  • Now I have tested the allocation which only write 0D,89,  B0, B1, B2, B3, C3 as the datasets in attached file, also I have read regs to verify that the values had been written in successfully. But it made no difference.

    Thanks for more advice.

  • Can you please post your schematics?

    I can't see anything obvious that would stop the output clock wiggling.

    BR,

    Steve

  • The attached file is our 5158 part.

    Thanks.

    3113.NEW_XH_5158.pdf

  • I can't see anything obviously wrong.

    I assume you have measured all your power supply pins on the TVP to make sure they are correct?

    Can you re-check that the schematic symbol generation is correct (i.e. that all pin numbers/names are correct etc...)?

    Can you confirm that you are looking at the output pin of the TVP with an oscilloscope to confirm that the clock is not oscillating, and not using the FPGA to determine the clock status?


    On a side note, I will be unavailable for a few weeks from now so responses will be slow. Sorry.

    BR,

    Steve

  • After power-up and reset the only register which needs to be written to enable the clock output is register B2h=25h

    Make sure your driver is not multiplying the address by 2x. The addresses stated already account for the read/write bit in the LSB but some driver code I have seen before assumes a shift is needed.

    Previously you said you were having trouble reading and writing registers reliably. Have you fixed these issues?

    BR,

    Steve

  • I have checked the problems you approved and they are all right. And now the trouble reading and writing regs dose not exit. 

    Do you have any test methods to locate the problem? Is it possible that the chip broke down?

    Thanks!

  • Now I find if I read regs immediately after write them, the values are what I want, but if I keep on reading operation,  the values will turn to default ones, for example, I write address 0xB2 = 0x25, the value read will turn 0x20 from 0x25 after a while.

    Also minutes later, I cannot write or read regs, and it will be ok after a reset operation.

    How to locate the problem?Thanks.

  • You have a power or signal integrity issue on your PCB.

    All I can suggest is to look very closely at your power supply and signal integrity of things like I2C, reset etc...

    BR,

    Steve