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Questions regarding TVP7002 External Clock

Jason(qx) Wang
Intellectual 500 points
Other Parts Discussed in Thread: TVP7002

Hi, Dear Guys:

According to the datasheet, TVP7002's external clock ( pin name= "EXT_CLK", pin number="80") can be ADC sample clock ( instead of the H-PLL generated clock), and also can be as a timing reference for the mode detection block (instead of the internal clock reference) at a typical 27MHz frequency.

My questions are:

1) If I set it as the ADC sample clock, and the sampling frequency is 24.55MHz, it's working?

2) Instead of recommended 27MHz, while set for the sampling clock, can I still set it as the timing reference in 24.55MHz?

I didn't find the description of conflicting in the Control Register Definitions if set the above two.

Thank you.

Jason 

 

  • 0
    TI__Genius 13460 points

    What  kind of video signal do you want to capture?

     

    BR,

    Eason

  • 0 in reply to Eason Wang
    Intellectual 500 points

    Hi, Eason:

    The video is VGA, 640x480, at 60 frame per second.

     

    Thank you.

    Jason Wang

  • 0 in reply to Jason(qx) Wang
    TI__Genius 13460 points

     www.ti.com/.../slec029

    The excel in it lists 4 different kinds of 640x480 format including 60 fps. The pixel clock is 25.175MHz, I think it should cover your case.

    Could you take a look at it?  It includes the recommend register values for the resolution/fps.

     

    BR,

    Eason

  • 0 in reply to Jason(qx) Wang
    TI__Mastermind 43875 points

    Jason,

    You cannot use an external clock when capturing a video signal. The external clock is for generic ADC modes.

    With real video signals the internal PLL is locked to the incoming h-sync signals.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Intellectual 500 points

    Hi, Steve:

    In the TVP7002 datasheet, there are many places, External Clock ( pin name=EXT_CLK, pin number=80) is mentioned to be alternatively as video sampling clock. Below are two examples.

    1) Page 4, Table 1:

    "External clock input. May be used as a timing reference for the mode detection block instead of

    the internal clock reference. May also be used as the ADC sample clock instead of the H-PLL

    generated clock."

    2) Page 37,  Subaddress 1Ah, Bit 1, PCLK_SEL,

    "PCLK SEL: Pixel clock selection. When the external clock input (pin 80) is selected as the ADC sample clock, the external clamp pulse

    (pin 76) should also be selected (Bit 7 of subaddress 0Fh).

    0 = ADC samples data using external clock input (pin 80)

    1 = ADC samples data using H-PLL generated clock (default)

    NOTE: The external clock input can also be selected as the reference clock for the Sync Processing block (see bit 3)."

    Thank you so much.

    Jason

  • 0 in reply to Jason(qx) Wang
    TI__Mastermind 43875 points
    It CAN be used as a sample clock, but it will not be phase aligned, unless it is externally phase locked to the h-sync.

    Regarding the timing reference, this is what it is really intended for. The internal 6MHz reference oscillator is not accurate enough, nor does it have enough resolution, to fully determine all VESA graphics modes. A higher frequency external clock allows this.

    It is not intended as a normal operating condition to use the external clock for the sampling clock.

    The internal PLL generated clock is both phase locked and phase aligned to the h-sync. An externally supplied clock will not be.

    Why do you need to use the external clock?

    BR,
    Steve
  • 0 in reply to Steve Clynes
    Intellectual 500 points
    Hi, Steve, firstly thank you so much.

    My design is described briefly as below.

    1) Main parts are Camera, TVP7002 and FPGA.

    2) Camera outputs video ( around 640x480), TVP7002 does AD converting, FPGA controls Camera and TVP7002 while receives digital video data from TVP7002.

    3) Camera's timing such as H-Sync, V-Sync, Trig (when Camera starts Exposure, when outputs video, etc. ) are controlled by FPGA. And analog video's structure such as numbers of pixels/per H-line, h-lines, V-frames) is known.

    4) TVP7002's timing such as HSync/ VSync , External Clock (actually all digital input and outputs) can be controlled and received by FPGA if needed.

    5) In one word, all timing can be known by FPGA. So, in the Function Block Diagram (page 2 of TVP7002 datasheet), the lower potion (Timing Processor and Clock Generation) almost can be ignored for the design. We just need that 10-bit ADC in the upper potion.

    6) One of approaches for the design can be: FPGA simply outputs a clock for sampling clock through TVP7002's EXT_CLK pin, and FPGA receives digital video data from TVP7002, all timings are controlled by FPGA including when the pixel data are effective, and how to adjust phase of sampling clock. Set TVP7002's Timing/Clock potion power down.

    7) Since I2C is a must, so the above approach is okay if the internal 6.5MHz is okay for the I2C timing.

    Best.

    Jason
  • 0 in reply to Jason(qx) Wang
    TI__Mastermind 43875 points
    Jason,
    In your case using the external clock source should be good, I agree.
    BR,
    Steve