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THS8200 Generating tri-level sync

Da Mil
Prodigy 110 points
Other Parts Discussed in Thread: THS8200

Hi!

I need to generate tri-level sync with the THS8200 without any input to sync to - our device is the master. I've managed to generate the color bar test pattern, but don't see anything that resembles the tri-level sync. Then I read in another post that the THS8200 has issues generating negative amplitude syncs in color bar mode.

Is there another way in achieving my goal with this device?

Thanks in advance for any insight!

  • 0
    TI__Genius 13460 points
    HI ,
    Why are you want to do so?
    Is it just for test ?
    Could you share the register dump?

    BR,
    Eason
  • 0 in reply to Eason Wang
    Prodigy 110 points
    Hi!

    Yes, it's for testing purposes as of now, but it's an important part.

    This is the latest register setting I've tried, mostly derived from the forum:

    REG 0x03 = 0xA3; // chip_ctl VESA Color Bars enabled
    REG 0x19 = 0xBD; // csc_offset3
    REG 0x34 = 0x05; // dtg_total_pixel_msb 1312; total pix/line
    REG 0x35 = 0x20; // dtg_total_pixel_lsb
    REG 0x36 = 0x00; // dtg_linecnt_msb
    REG 0x37 = 0x01; // dtg_linecnt_lsb
    REG 0x38 = 0x87; // dtg_mode VESA Mode
    REG 0x39 = 0x33; // dtg_frame_field_msb 800; total lines/frame
    REG 0x3A = 0x20; // dtg_frame_size_lsb
    REG 0x3B = 0x20; // dtg_field_size_lsb
    REG 0x3C = 0x80; // dtg_vesa_cbar_size 128pix;/bar (1024;/8)
    REG 0x70 = 0x88; // dtg_hlength_lsb HSOUT width=136; pixels
    REG 0x71 = 0x00; // dtg_hdly_msb
    REG 0x72 = 0x01; // dtg_hdly_lsb
    REG 0x73 = 0x07; // dtg_vlength_lsb
    REG 0x74 = 0x00; // dtg_vdly_msb
    REG 0x75 = 0x01; // dtg_vdly_lsb
    REG 0x76 = 0x00; // dtg_vlength2_lsb;
    REG 0x77 = 0x07; // dtg_vdly2_msb;
    REG 0x78 = 0xFF; // dtg_vdly2_lsb;
    REG 0x79 = 0x00; // dtg_hs_in_dly_msb
    REG 0x7A = 0x01; // dtg_hs_in_dly_lsb
    REG 0x7B = 0x00; // dtg_vs_in_dly_msb
    REG 0x7C = 0x01; // dtg_vs_in_dly_lsb
    REG 0x82 = 0x5f; // pol_cntl +HS+VS ouputs
    REG 0x1D = 0x00;
    REG 0x1E = 0x49;
    REG 0x1F = 0xB6;
    REG 0x20 = 0x00;
    REG 0x21 = 0x00;
    REG 0x22 = 0x00;
    REG 0x23 = 0x23;
    REG 0x24 = 0x2A;