TVP5150 question -27Mhz clk

DANIELE COZZI

- Datasheet say “The ADC has nine bits of resolution and runs at a nominal speed of 27 MHz. The clock input for the ADC comes from the horizontal PLL”: so I deduce that if the video input is not present the horizontal PLL can not lock so also the 27MHz is not present. Is it true?

- If I set the Power-down mode bit on Operation Mode Control Register “ADCs are turned off and internal clocks are reduced to minimum”: in this situation the 27MHz is switched off?

- The Power-down mode activated with the register has the same effect of the PDN pin?

- It’s possible to stop the main oscillator (the 14.31818MHz external quartz)?

thank you

over 7 years ago

0 Steve Clynes over 7 years ago

TI__Mastermind 43875 points

With no video input the output PClk will free run at a nominal 27MHz.

I believe the PDN pin and PDN control bit behave in the same manner but I don't know if the 27MHz is disabled or not.

The oscillator cannot be turned off I don't think.

BR,
Steve

0 DANIELE COZZI over 7 years ago in reply to Steve Clynes

TI__Expert 4070 points

Hello Steve,

is it possibl;e to verify if with PDN pin and bit the internal 27Mhz clock uis disabled ?

Thank you

0 Steve Clynes over 7 years ago in reply to DANIELE COZZI

TI__Mastermind 43875 points

Unfortunately there are no longer any support resources available for the TVP line of products.

Even my support here on the forums is limited unfortunately.

BR,

Steve

0 Steve Clynes over 7 years ago in reply to Steve Clynes

TI__Mastermind 43875 points

On a side note... What is your main concern about the internal clock being disabled?

If it is about reducing power then the power numbers in the datasheet are valid for each condition regardless of what the actual internal state of the clock is.

If you want to enable/disable the external clock pin then you can do that manually through the clock output enable control bit.

BR,
Steve

0 DANIELE COZZI over 7 years ago in reply to Steve Clynes

TI__Expert 4070 points

Hello steve,
the concerns is related to the EMI, since they are having an isuse related to the Video decoder, they would like to understand if there are possibilities to disable th internal CLK generator to reduce the EMI noise

0 Steve Clynes over 7 years ago in reply to DANIELE COZZI

TI__Mastermind 43875 points

EMI is usually a layout issue. Is there a good, solid ground plane under the TVP and all connected signals? Are the power supply pins decoupled correctly? Can the customer remove power to the TVP to verify that the TVP is really where the EMI is coming from?

It seems like reducing EMI only when the decoder is disabled is a bit redundant since I would assume that the EMI still exists when the decoder is active? EMI certification requires passing in all conditions hence reducing only when disabled would still fail certification.

BR,
Steve

0 DANIELE COZZI over 7 years ago in reply to Steve Clynes

TI__Expert 4070 points

Steve,
I just need to reply about our Video decoder,
I would like to understan if the internal CLK can be disabled or not .
The project is already in production

0 Steve Clynes over 7 years ago in reply to DANIELE COZZI

TI__Mastermind 43875 points

As I mentioned I can't verify one way or the other. I don't have hardware available.

If the noise is definitely coming from the TVP and setting the PDN pin does not make the EMI go away then I would say "no".

BR,
steve

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TVP5150 question -27Mhz clk