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TVP5158 Not sending data to Host

RAJ.M
Expert 2440 points
Other Parts Discussed in Thread: TVP5158

Hi All,

I am using TVP5158 Video decoder with Custom board. I can Download Patch successfully to tvp5158.

I use 4CH but for testing i give one analog input(From TV) to tvp51578. its detect the video successfully but output vin[0-7] and vin_clk is low [probed using oscilloscope] 

This is my log

[m3vpss ] 8307: CAPTURE: VIP 0: VID DEC 1024 (0x58): Video Standard Detect in Progress !!!
[m3vpss ] I2C0: DEV 0x58: WR 0xff = 0x01
[m3vpss ] I2C0: DEV 0x58: RD 0x00 = 0x7e
[m3vpss ] I2C0: DEV 0x58: RD 0x01 = 0x80
[m3vpss ] I2C0: DEV 0x58: RD 0x0c = 0x82
[m3vpss ] 8408: CAPTURE: Detected video (720x288@50Hz, 1)!!!

[m3vpss ] 8445: CAPTURE: VIP0 PortA capture mode is [ 8-bit, Pixel-mux Embedded Sync] !!!
[m3vpss ] I2C0: DEV 0x58: RD 0x08 = 0x51
[m3vpss ] I2C0: DEV 0x58: RD 0x09 = 0x58
[m3vpss ] I2C0: DEV 0x58: RD 0x04 = 0x02
[m3vpss ] I2C0: DEV 0x58: RD 0x05 = 0x00
[m3vpss ] I2C0: DEV 0x58: RD 0x06 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xc0 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xc4 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xc8 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xc3 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
[m3vpss ] I2C0: DEV 0x58: RD 0xc1 = 0x88
[m3vpss ] I2C0: DEV 0x58: RD 0xc2 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xc1 = 0x55
[m3vpss ] I2C0: DEV 0x58: WR 0xc2 = 0x55
[m3vpss ] 8561: CAPTURE: VIP 0: VID DEC 1024 (0x58): 5158:0002:0000, AUD_STATUS 0
[m3vpss ] CAPTURE::HEAPID:0 USED:224
[m3vpss ] 8561: CAPTURE: Create Done !!!
[m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xe8 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe9 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xea = 0xb0
[m3vpss ] I2C0: DEV 0x58: RD 0xe0 = 0x00
[m3vpss ] TVP5158: 0x58: Downloading patch ...

[m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xe8 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe9 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xea = 0xb0
[m3vpss ] I2C0: DEV 0x58: WR 0xe0 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe8 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe9 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xea = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb5
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x09
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x13
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd3
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x05
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xa9
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x06
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x06
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x25
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x29
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x96
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x38
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x41
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x71
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x22
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x82
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x71
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x36
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x30
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x41
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x75
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x18
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x49
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x19
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x49
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x19
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x49
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf9
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x26
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x30
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe7
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x17
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x29
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x71
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x05
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc6
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x31
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x69
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x31
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x61
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfd
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfd
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x58
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x30
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x49
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x22
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfd
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfe
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf6
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe7
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x46
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x63
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xa4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x28
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x89
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe5
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x55
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf8
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x57
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x58
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x89
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x44
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x33
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb5
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x30
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xec
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe8
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfd
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x79
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe2
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xde
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x65
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x27
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x77
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x11
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x81
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x87
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc3
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x98
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x10
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x71
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xcc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc8
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf2
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xbe
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xba
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x28
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x94
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xff
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x35
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xaf
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x30
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x28
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x62
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x65
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xa8
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x64
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xa4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x09
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x62
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x49
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x95
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x91
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x8d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x87
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x89
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfe
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x24
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x59
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd3
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x57
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x39
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xcd
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x55
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc7
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x38
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x41
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x50
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x51
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x49
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xca
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc9
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb9
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x42
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x05
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x33
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x19
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x62
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x49
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb9
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x42
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x05
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x31
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x26
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x34
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x38
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x84
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x86
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x8a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x8c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x8e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x90
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x92
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x94
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x96
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x98
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x9a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb8
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xba
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfa
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xbd
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb5
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xff
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf7
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x19
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xff
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xbd
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x24
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x33
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x22
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x33
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb5
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x87
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x29
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x22
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd5
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x27
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x13
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x74
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x22
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x22
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x26
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x33
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x13
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x74
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x42
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x22
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x33
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x13
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x31
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe8
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x90
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x66
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x46
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x76
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x09
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc9
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x36
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x71
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x06
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x9f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf8
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc8
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x21
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x31
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x91
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x05
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x30
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x18
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x90
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x12
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x89
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x89
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x8b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x81
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x05
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x89
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x19
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x81
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x28
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x76
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x05
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x76
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xac
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x76
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x05
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe8
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x76
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xbd
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x50
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x10
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x80
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x9e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x30
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x50
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x74
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x46
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x28
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x27
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x27
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x16
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x86
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x16
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x74
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x28
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x05
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x12
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x11
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x12
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x10
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x43
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xdb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x11
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xdb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x09
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x64
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x83
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x84
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x9c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x9d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x64
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x44
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x84
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x44
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x94
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x85
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x89
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x23
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xbc
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x42
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xaa
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xc4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x89
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x94
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x42
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x25
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xdb
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x9c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0b
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x94
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x18
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x9a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x25
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x55
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x06
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x35
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xbd
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x85
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x85
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x89
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x45
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x19
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x27
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd2
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x07
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x32
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xaa
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x84
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe4
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x06
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x27
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x85
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x89
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x3d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x0c
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x38
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x49
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x22
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x8a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x5e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x41
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x6a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x46
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x7d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x03
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xd1
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x11
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x41
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x69
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x1a
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x19
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x02
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x11
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x41
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x69
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x18
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x19
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x74
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x40
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x44
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x75
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xe0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xbd
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xf0
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xb5
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x32
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x78
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x88
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x05
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x15
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x49
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x08
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x30
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x01
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x24
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x04
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x70
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xa6
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x46
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2f
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfe
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x44
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x47
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xa6
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x46
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x48
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xfe
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x44
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x00
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x47
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x4d
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x2e
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0x68
[m3vpss ] I2C0: DEV 0x58: WR 0xe1 = 0xa6
[m3vpss ] TVP5158: 0x58: Downloading patch ... DONE !!!

[m3vpss ] I2C0: DEV 0x58: RD 0x08 = 0x51
[m3vpss ] I2C0: DEV 0x58: RD 0x09 = 0x58
[m3vpss ] I2C0: DEV 0x58: RD 0x04 = 0x02
[m3vpss ] I2C0: DEV 0x58: RD 0x05 = 0x03
[m3vpss ] I2C0: DEV 0x58: RD 0x06 = 0x02
[m3vpss ] TVP5158: 0x58: 5158:0002:0302

[m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xb0 = 0x60
[m3vpss ] I2C0: DEV 0x58: WR 0xb1 = 0x17
[m3vpss ] I2C0: DEV 0x58: WR 0xb2 = 0x20
[m3vpss ] I2C0: DEV 0x58: WR 0x0e = 0xff
[m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
[m3vpss ] I2C0: DEV 0x58: WR 0xba = 0x01

Regards,

RAJ M

  • 0
    TI__Mastermind 43875 points

    I would start simple and omit patch download. This should only be necessary if the patch provides a feature or improvement that is critical to your application.

    Start by using all defaults, then add in the following...

    Register 0xB2 (see data manual for details on channel requirements for this register)
    Enable video port b (Video_Port_B_En)
    Enable clock outputs (Out_CLK_P_En/Out_CLK_N_En)

    Check that the clock is wiggling.

    Once the clock is operational start adding back your specific settings and then patch code is desired.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Expert 2440 points

    Hi Steve,

    Thanks for your reply,

    I did what you suggest i got clock  output its 108Mhz .I am using Out_CLK_P_En, This is my output port

    DVO_A0 
    DVO_A1 
    DVO_A2 
    DVO_A3 
    DVO_A4 
    DVO_A5 
    DVO_A6 
    DVO_A7

    Out_CLK_N_En grounded in my schematic.

    What i have to do next??

    I have one more doubt if all four channel is getting input then only tvp5158 send data [vin0-7]??

    This is my Log


    [m3vpss ] 7301: CAPTURE: VIP 0: VID DEC 1024 (0x58): Video Standard Detect in Progress !!!
    [m3vpss ] I2C0: DEV 0x58: WR 0xff = 0x01
    [m3vpss ] I2C0: DEV 0x58: RD 0x00 = 0x7e
    [m3vpss ] I2C0: DEV 0x58: RD 0x01 = 0x80
    [m3vpss ] I2C0: DEV 0x58: RD 0x0c = 0x82
    [m3vpss ] 7401: CAPTURE: Detected video (720x288@50Hz, 1)!!!
    [m3vpss ] 7438: CAPTURE: VIP0 PortA capture mode is [ 8-bit, Pixel-mux Embedded Sync] !!!
    [m3vpss ] I2C0: DEV 0x58: RD 0x08 = 0x51
    [m3vpss ] I2C0: DEV 0x58: RD 0x09 = 0x58
    [m3vpss ] I2C0: DEV 0x58: RD 0x04 = 0x02
    [m3vpss ] I2C0: DEV 0x58: RD 0x05 = 0x00
    [m3vpss ] I2C0: DEV 0x58: RD 0x06 = 0x00
    [m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
    [m3vpss ] I2C0: DEV 0x58: WR 0xc0 = 0x00
    [m3vpss ] I2C0: DEV 0x58: WR 0xc4 = 0x00
    [m3vpss ] I2C0: DEV 0x58: WR 0xc8 = 0x00
    [m3vpss ] I2C0: DEV 0x58: WR 0xc3 = 0x60
    [m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
    [m3vpss ] I2C0: DEV 0x58: RD 0xc1 = 0x88
    [m3vpss ] I2C0: DEV 0x58: RD 0xc2 = 0x88
    [m3vpss ] I2C0: DEV 0x58: WR 0xc1 = 0x55
    [m3vpss ] I2C0: DEV 0x58: WR 0xc2 = 0x55
    [m3vpss ] 7554: CAPTURE: VIP 0: VID DEC 1024 (0x58): 5158:0002:0000, AUD_STATUS 0
    [m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
    [m3vpss ] I2C0: DEV 0x58: WR 0xe8 = 0x60
    [m3vpss ] I2C0: DEV 0x58: WR 0xe9 = 0x00
    [m3vpss ] I2C0: DEV 0x58: WR 0xea = 0xb0
    [m3vpss ] I2C0: DEV 0x58: RD 0xe0 = 0x00
    [m3vpss ] TVP5158: 0x58: NO Patch downloaded, using ROM firmware.
    [m3vpss ] I2C0: DEV 0x58: RD 0x08 = 0x51
    [m3vpss ] I2C0: DEV 0x58: RD 0x09 = 0x58
    [m3vpss ] I2C0: DEV 0x58: RD 0x04 = 0x02
    [m3vpss ] I2C0: DEV 0x58: RD 0x05 = 0x00
    [m3vpss ] I2C0: DEV 0x58: RD 0x06 = 0x00
    [m3vpss ] TVP5158: 0x58: 5158:0002:0000
    [m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
    [m3vpss ] I2C0: DEV 0x58: WR 0xb0 = 0x60
    [m3vpss ] I2C0: DEV 0x58: WR 0xb1 = 0x17
    [m3vpss ] I2C0: DEV 0x58: WR 0xb2 = 0xa4
    [m3vpss ] I2C0: DEV 0x58: WR 0x0e = 0xff
    [m3vpss ] I2C0: DEV 0x58: WR 0xfe = 0x0f
    [m3vpss ] I2C0: DEV 0x58: WR 0xba = 0x01

    Regards,

    RAJ M

  • 0 in reply to RAJ.M
    TI__Mastermind 43875 points

    Unfortunately support for this device is extremely limited (hence the NRND status) so I can only make best guess suggestions since I have not worked with this particular device much.

    How are you trying to use the device? It is a 4 channel decoder that can either operate as 4 independent channels, or combine multiple channels into a single data stream.

    Device configuration depends on how you are using the channels.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Expert 2440 points

    Hi Steve,

    Thank you for your reply

    I got output. tvp5158 sending data to my display now.

    Regards,

    RAJ M

  • 0 in reply to RAJ.M
    TI__Mastermind 43875 points

    Fantastic.

    What was the solution?

    BR,

    Steve