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TVP5158: OCLK connection to the processor

Part Number: TVP5158

Hi

In TVP5158 non interleaved mode, I need to connect all the data lines to DM8147 video input pins Vin0_A_D[0:7], Vin0_A_D[8:15], Vin1_A_D[0:7], Vin1_B_D[0:7].

In DM8147 Processor, I will be using Vin0 channel in dual 8-bit mode, and Vin1 channel A and B ports.

In this case, Is it ok if I connect OCLK to the Vin0_A_clk. Vin0_B_clock, Vin1_A_clk and Vin1_B_clock of the processor through a 0E resistor, or any special care(ex: using a buffer) should be considered?

Thanks in advance. Awaiting your quick reply.

Regards

Sushruta

  • Unfortunately I can't comment on the DM8147 input clock requirements, but in terms of output drive capability of the TVP clock, I would certainly suggest at least having the option for a high speed buffer on the clock line which you can replace with a 0R resistor if the buffer is not necessary.

    BR,

    Steve

  • Hi Steve

    Thank you for your reply.

    Can you please suggest a suitable clock buffer. Also, let us know if this affects the functionality(ex: clock and data mismatch due to clock delay).

    Regards

    Sushruta

  • The exact buffer depends very much on your specific system design.

    Adding a buffer will certainly delay the clock but again this is very dependent on the specific buffer used.

    You will need to review various buffers which have the correct bandwidth (depends on your configuration), drive strength (depends on your layout and system level loading) and propagation delay spread (depends on your system devices, loading, setup/hold requirements, clock polarity requirements etc...)

    BR,

    Steve