TVP70025I register setting problem

Jack,

Does your TFT require HS, VS, and DE for synchronization?  Try the XGA60Hz register settings below for starters.  You may have to change the output sync polarites in REG0Eh to match what the panel needs.

WR_REG,TVP7000,0x01,0x01,0x54 // PLL DIVMSB 1344 pix/line                
WR_REG,TVP7000,0x01,0x02,0x00 // PLL DIVLSB                 
WR_REG,TVP7000,0x01,0x03,0x58 // PLL CONTROL                
WR_REG,TVP7000,0x01,0x04,0x80 // PHASE SEL(5) CKDI CKDI DIV2
WR_REG,TVP7000,0x01,0x05,0x06 // CLAMP START                
WR_REG,TVP7000,0x01,0x06,0x10 // CLAMP WIDTH
WR_REG,TVP7000,0x01,0x07,0x88 // HSYNC OUTPUT WIDTH - 136
WR_REG,TVP7000,0x01,0x0E,0x00 // SYNC CONTROL    HSout- VSout-
WR_REG,TVP7000,0x01,0x0F,0x2E // PLL and CLAMP CONTROL bit0 (0=  HSPO by chip)
WR_REG,TVP7000,0x01,0x10,0x58 // SOG Threshold-(RGB Clamp)
WR_REG,TVP7000,0x01,0x11,0x40 // Sync Separator Threshold
WR_REG,TVP7000,0x01,0x12,0x01 // PRE_COAST                  
WR_REG,TVP7000,0x01,0x13,0x00 // POST_COAST
WR_REG,TVP7000,0x01,0x15,0x04 // Output Formatter

WR_REG,TVP7000,0x01,0x17,0x10 // MISC Control 2  DE out, Enable Outputs
WR_REG,TVP7000,0x01,0x18,0x01 // Clock polarity
  
WR_REG,TVP7000,0x01,0x19,0xAA // INPUT MUX SELECT,    RGB CH3 selected      
WR_REG,TVP7000,0x01,0x1A,0xC2 // INPUT MUX SELECT, HSYNC_A and VSYNC_A selected, SOG and Clamp Filter
WR_REG,TVP7000,0x01,0x21,0x0D // HSOUT START
WR_REG,TVP7000,0x01,0x22,0x00 //               
                
WR_REG,TVP7000,0x01,0x26,0x80 // ALC RED and GREEN LSB      
WR_REG,TVP7000,0x01,0x28,0x53 // AL FILTER Control          
WR_REG,TVP7000,0x01,0x2A,0x07 // Enable FINE CLAMP CONTROL
WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL-SOG ON
WR_REG,TVP7000,0x01,0x2C,0x50 // ADC Setup
WR_REG,TVP7000,0x01,0x31,0x18 // ALC PLACEMENT
WR_REG,TVP7000,0x01,0x35,0x00 // VSout Align
WR_REG,TVP7000,0x01,0x36,0x00 // Sync Bypass
WR_REG,TVP7000,0x01,0x3D,0x06 // Line Length Tolerance (Pixel Tolerance)
//DE
WR_REG,TVP7000,0x01,0x40,0x33 // AVID Start  307 (296+11)
WR_REG,TVP7000,0x01,0x41,0x01 // AVID Start 
WR_REG,TVP7000,0x01,0x42,0x33 // AVID  Stop 1331 ((307 +1024 ) ok
WR_REG,TVP7000,0x01,0x43,0x05 // AVID Stop
WR_REG,TVP7000,0x01,0x44,0x03 // VBLK F0 Offset (3)
WR_REG,TVP7000,0x01,0x45,0x03 // VBLK F1 Offset
WR_REG,TVP7000,0x01,0x46,0x26 // VBLK F0 Duration  38 lines
WR_REG,TVP7000,0x01,0x47,0x26 // VBLK F1 Duration

Hi Larry,

Thank you for your attention about my problem. it show below :

with this setting I have a damaged image on my TFT

VGA:

LVDS:

and my TFT need DE,HS,VS. so when I edit this section image change but never good!!!

//DE
WR_REG,TVP7000,0x01,0x40,0x33 // AVID Start  307 (296+11)
WR_REG,TVP7000,0x01,0x41,0x01 // AVID Start 
WR_REG,TVP7000,0x01,0x42,0x33 // AVID  Stop 1331 ((307 +1024 ) ok
WR_REG,TVP7000,0x01,0x43,0x05 // AVID Stop
WR_REG,TVP7000,0x01,0x44,0x03 // VBLK F0 Offset (3)
WR_REG,TVP7000,0x01,0x45,0x03 // VBLK F1 Offset
WR_REG,TVP7000,0x01,0x46,0x26 // VBLK F0 Duration  38 lines
WR_REG,TVP7000,0x01,0x47,0x26 // VBLK F1 Duration

Please explain for me what is this registers and how it set?

what is te 307,296,11,1331?

instead of 1331 , 1344 is better ( according to datasheet - horizental periud ) ? when I edit it and use 768 ( vertical periud ) instead of 1331 , the result is better.why?

other registers can solve this problem? ( I change polarity of hs,vs,clk but it is not good )

Best Regards

Jack,

AVID start and stop define the DE horizontal active interval wich should be 1024 pixels for XGA.  AVID start is calculated from a fixed delay factor (11), sync width (136 for XGA60Hz) , and horizontal backporch (160 for XGA60Hz).

Vertical DE timing is set up using VBLNK offset and duration.  Duration should be the number of line in vergtical blanking ( 38 for XGA60Hz). 

What input format is present at the TVP input?  This setup requires an XGA60Hz input at the TVP70025 input.  If another input format is used with these setings the lines per frame and pixel clock will not be correct.

You may also want to check the clock polarity setup, to make sure the correct clock edge is being used throughout the link.

Hi larry,

I set resolution 1024x768 60hz in WIN XP and connect the output of this port ( VGA ) at first to another LCD and in its OSD Menu I see 1024x768 60hz 48khz .in next step I connect this port to my board but i saw that image ( image in previous post )

fixed delay factor = 11 is a standard value for XGA60hz?

according to these TFT spec, value of any register must be change ?

what is your idea? I only change AVID and VBLNK and leave other register with many try & test to find best value o fit image in my TFT?

and what is your idea about :

instead of 1331 , 1344 is better ( according to datasheet - horizontal cycle) ?

when I edit  AVID registers, after change value and use 806 ( vertical cycle) instead of 1024, the result is better.why?

I read "806" from "Lines Per Frame Status" register.This seems to have the correct

but I read sometimes "133" from "Clocks Per Line Status" register and soemtimes "134".why?

133 => 48.872 khz  and 134 => 48.507 khz . is it important ?

I don't remember the value of "HSYNC Width" register and 'VSYNC Width" register. Do you know the right value for these registers? If you know write for me ,I check them as soon as possible.

Best Regards

Best Regards

Jack,

fixed delay factor = 11 is a standard value for XGA60hz?

>This delay is for delay matching in the TVPsync path and should stay the same for all graphics setups. Sync width and backporch setting will change for the various formats, however, so AVID start will change.

according to these TFT spec, value of any register must be change ?

>The panel specs agree with XGA60Hz, so the AVID and VBLNK settings I sent should be OK.

what is your idea? I only change AVID and VBLNK and leave other register with many try & test to find best value o fit image in my TFT?

and what is your idea about :

instead of 1331 , 1344 is better ( according to datasheet - horizontal cycle) ?

> I would stay with 1331.  There are some potential issue with 1344.  I will send info on that tomorrow.

when I edit  AVID registers, after change value and use 806 ( vertical cycle) instead of 1024, the result is better.why?

> AVID start/stop is horizontal timing, not vertical. 806 may look different but is not correct.

but I read sometimes "133" from "Clocks Per Line Status" register and soemtimes "134".why?

133 => 48.872 khz  and 134 => 48.507 khz . is it important ?

> Not important, there will be some variation.

I don't remember the value of "HSYNC Width" register and 'VSYNC Width" register. Do you know the right value for these registers? If you know write for me ,I check them as soon as possible.

> HSYNC width for XGA60 is 136 pixels, VSYNC width is 6 lines.  HSYNC width can be adjusted in the TVP, but VSYNC cannot. VSOUT out should be the same width as VSYNC input.

You the AVID and VBLNK settings I sent, you might try changing CLK POL bit in REG 18h.  Also try VSYNC Alignment change in REG35h to align VS with HS.  The panel may be sensitve to this.

Can you sen the complete spec of the panel?

Hi Larry,

This is data sheet of my TFT :

8867.TFT.pdf

I read this value from chip :

Hsync width (0x3B) = 0x16=22    <> 136

Vsync width (0x3C) =0x03=3        <> 6

it is different from your data. it is related to what kind of reason ?

I found some information about AVID and VBLK  in manual of TVP7002 EVM and I use it but these data don't work for me.

I edit value of CLK POL in 0x18 ( also test other bit in this register ) and value of align in 0x35 ( 0x00 , 0x10 , 0x20 , ...., 0xff ) .but they don't have a good result.

I see in the TVP7002 EVM schematic file, there is a DUAL SCHMITT-TRIGGER BUFFER ( SN74LVC2G17 ) on the Hsync & Vsync line of  VGA port. but I don't have this part so I used NC7WZ16.it is a UHS DUAL BUFFER ( UHS = Ultra High Speed ) and I see it used in another board on Hsync & Vsync line ( of course on that board VGA was a output port  ). SCHMITT-TRIGGER is very necessary ? is it very important ?

TVP7002 EVM schematic file:

SN74LVC2G17 datasheet :

NC7WZ16 datasheet :

Best Regards

Hi,

If my TFT work only with DE , what is change ?

Please anybody answer my questions. I necessary need this answers.

Jack,

"I read this value from chip :

Hsync width (0x3B) = 0x16=22    <> 136

Vsync width (0x3C) =0x03=3        <> 6

it is different from "your data". it is related to what kind of reason ?

> What does "your data" refer to?  Clocks per line and HSYNC width status readback will vary some due to precision of the REFCLK.

> A Schmitt trigger could help when noise is present.  Look at DATACLK out relative to HSYNC_IN to se if the PLL is locked to HSYNC.  If the clock is stable at 65MHz and phase locked to HSYNC_IN, then the HSYNC input path is OK.

>Your panel looks OK for XGA60Hz format and appears to use DE timing.  The TVP70025 setup that I sent you should output DE on pin 22.  There is a limitation in the TVP7002 DE generation that may be upsetting your panel.  The last active line of the frame will be missing approximately 4 pixels before the vertical blanking interval begins.  I am not sure if your panel could be sensitive to this. 

Is the panel display rolling or stationary with a lot of noise?

Hi Larry,

"your data" refer to :

> HSYNC width for XGA60 is 136 pixels, VSYNC width is 6 lines.  HSYNC width can be adjusted in the TVP, but VSYNC cannot. VSOUT out should be the same width as VSYNC input.

َAnyway below item is true ?

Hsync width (0x3B) = 0x16=22

Vsync width (0x3C) =0x03=3

If not.what is wrong ?

If the clock is stable at 65MHz and phase locked to HSYNC_IN, then the HSYNC input path is OK. How can I trust it done ?

panel display rolling with a lot of noise , and when connect a 1024*768,60hz to this chip I see an image that show only a part of top section of image.It is appear that original image create in larger size and my TFT only show this section, of course with rolling and a lot of noise.

With your setting when I measure frequency of Dataclk output and HSYNC output with Oscilloscope on my board , I see 103MHz ( instead of 65MHz ) on Dataclk and 76KHz ( instead of 48 KHz ) on HSYNC !!! why ?

Best Wishes

Hi,

I'm checkong the :

1- output internal ref clk and it is = 6.33 MHz

2- input and output of buffer on VGA hsync and vsync and both of them was clear and sharp

3- I read value of HPLL register and I sure write process of this register  is True ( read value same as write value )

4- I use an 27 MHz external osc and set CLK SEL in Input Mux Select 2 ( 0xCA instead of 0xC2 ) but it didn't change any thing !

5- I check value of resistor and capacitors in Horizontal PLL Loop Filter , and it is same as Figure 4 in page 15 of datasheet

now , what can I do ?

Best Regards

Jack,

It seems like the input format is not XGA60Hz or there is an issue with you input MUX selection.

Are you using separaste HSYNC/VYSNC input or SOG.  IF the HSYNC input is 48.36KHz and the PLL is set up correclty, the ouput clock should be 65MHz.

Are you power supplies all clean and decoupled well?

Regarding HS/VS stastus readback:

With external 27M REFCLK I get:

HS width (REG3Bh) = 56 (38h)

VS width (REG 3Ch) = 06

With internal REFCLK I get:

HS width (REG3Bh) = 13 (0Dh)

VS width (REG 3Ch) = 5-6

There will be some part to part variation in internal REFCLK, so the HS reading will vary.

The input MUX settings that I sent you may not be correct for your board design.  You may want to check this.  I would focus on input format HSYNC 48.3K rate, PLL setting, Mux setting, and then 65MHz ouput clock.

Hi,

I'm using Input Mux Select 1=0x00 for choosing SOGIN_1,RIN_1,GIN_1,BIN_1 and use Input Mux Select 2=0xC2 or 0xCA for VSYNC_A input,HSYNC_A input

input format set in windows XP ( resolution = 1024x768 60 Hz ) and I think that I saw 48KHz ( with oscilloscope ) on HSYNC on input buffer.

my circuite :

I read :

HSD =1 = HSYNC activity detected

AHS =0 = HSYNC from selected HSYNC input

VSD =1 = VSYNC activity detected

AVS =0 = VSYNC from selected VSYNC

Looks correct.  With 48KHz HSYNC, the ouput clock should be 65MHz, if sthe PLL is programmed for XGA60Hz.. 

Setting HS BP = 1 in Reg36h, will route HSYNC in, as seen by the TVP, directly to HSOUT.  HSOUT should the be 48.3K.

There may be an issue with the TVP part, or your board.  Do all of the power suppies look OK?

I would continue to focus on HSYNC in frequency and clock ouput frequency.

All, check to see if REG 3Dh = 6, REG 22h= 0, and keep PCLK SEL = 1 in REG 1Ah..

Hi Larry,

After I test value of all register and see all of them are True. so for a test I repair solder of chip and clean board again and when power up board I see image size is good and I see image in two model of TFT 10.4 XGA.

Thank you so much

of course the color of image is noisy but I think is not accorfing to TVP70025I chipset and is according to  SN65LVDS84AQ ( LVDS Transmitter )

my TFT image view :

How can I clean my image from this noise? my PCB have 2 Layers , if I design a 4 layer PCB with ground plane and  power plane in mid layers this board work good and noise remove from image or another solution may be used in this problem?

How can automatically determine the format of VGA input signal and set proper value for HPLL and ....registers ?

Best Regards

Jack,

It is good to hear that you are making progress.  A 4-layer PCB is preferred, but you may be able to make improvements before spinning a new board.  Check power supply noise and decoupling.  The PLL supply is critical for low jitter on the clock.  Adding addtional supply filtering could help.  Using external clean supply connections can help isolate supply noise issues.  A PCB layout guideline can be found at http://focus.ti.com/docs/prod/folders/print/tvp70025i.html.

Also try adjusting HPLL phase in REG 04h to see if the noise is related to ADC sampling phase.

Your panel has XGA60Hz native resolution and timing.  It will be dificult to support multiple formats without a scaler IC.

Hi,

After I working on power,clk and signal lines the noise of image removed and image quality is good.

but when I connect board to another device ( image contain number and graph in black background ( ECG monitor ) ) I saw a shadow in right of characters ( width < 1mm ) that blur image .how can sharp this image? ( with align , phase and contrast  it didn't better )

I saw in some device, frequency of hsync not equal to 48.3KHz  and for example = 47.9 KHz and perhaps my device have this problem how can fix it?

How can automatically set value of register according to input format and TFT type ( like AutoTunes in traditional LCD ) ?

Please tell me a part number for scaler ic .

Best Regards

Jack,

When switching device inputs, if the input is still XGA60 and it is being correctly sampled by the TVP, the shadow may be due to RGB input termination or signal integraity problems.  Make sure the the input trace are terrminated with 75-ohm.  Having a good ground plane under the RGB traces and having good trace impedance matcing could also help.

The 47.9KHz source may have been something other than XGA60.  A muit-format solution typically uses an automatic format dtection algorithm base on input sync rates, sync polarities, and sync widths.  The various TVP status regsisters can be used to identify the input format.

We don't have a stand-alone scaler IC.  You might check some of the MDIN-xxx devices from Macro Image Tech.  The output format needs to match the TFT spec.

Hi,

I change value of every register and put a 33 ohm resistor in series with red,green,blue,hsync and when i watch no change happened so restor all register value and parts to originally model at now I only montage a 750 ohm terminator at hsync input and 75 ohm terminator at red,green,blue input. and in next PCB I use a ground plane in mid layer .

but I'm not sure in next PCB my image will be sharp.

of course when I look in my image it look like be extraction to right of TFT. so do you have another idea to sharp image and fix image ( without extraction to right ) ?

Best Regards