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tvp5147m1
Related Posts

  • Forum Post: Composite video to RBG converter

    James McGloin
    Hi all, I am looking for suggestions on the cheapest way to convert NTSC/PAL video to drive a RGB LCD Regards James
    on Jun 3, 2010

  • Forum Post: Re: Composite video to RBG converter

    Larry Taylor
    Hi James, We provide NTSC/PAL video decoders (See TVP5150AM1, TVP5151, and TVP5147M1) that convert video to digital YCbCr. You will need to follow that with a device that will scale, de-interlace, and convert to RGB for display on the LCD panel. One of TI's ARM or DSP based processors used with...
    on Jun 4, 2010

  • Blog Post: New Application Note Releases

    Foe
    The following new TVP/THS application notes are now available from ( http://www.ti.com/ ). Literature Number Release Date Description SLEA073A August 2009 TVP5158 PCB Layout Guidelines SLEA075 September 2009 TVP5151 PCB Layout Guidelines SLEA076 June 2010 THS8134B PCB Layout Guidelines...
    on Jul 29, 2010

  • Forum Post: Vertical & Horizontal Sync Loss - TVP5147PFP

    Sornam Viswanathan V
    Hello, I have a custom board with a TVP5147PFP. I am using this to decode a B/W PAL signal. The input PAL signal seems to drive a monitor just fine. But when the same input signal is given to the TVP5147, i get a vertical and horizontal sync signal loss from status register 0X3A and there is no...
    on Jul 30, 2010

  • Forum Post: Re: Vertical & Horizontal Sync Loss - TVP5147PFP

    Larry Taylor
    Hi Sornam, Could you please try toggling the power save bit in REG 03h to see if it resolves this issue? Do you have pull-down resistors installed on Pins 69 and 71? This could affect the power-up state of the TVP5147M1 and is recommended. Regards, Larry
    on Jul 30, 2010

  • Forum Post: Re: Vertical & Horizontal Sync Loss - TVP5147PFP

    Larry Taylor
    Sornam, Were you able to resolve your lock issue? Regards, Larry
    on Aug 3, 2010

  • Forum Post: Re: Vertical & Horizontal Sync Loss - TVP5147PFP

    Sornam Viswanathan V
    Hello Larry, Sorry for the late response. Here are a few updates to my earlier post. a) On careful examination of the datasheet, i came to understand that the outputs (CLK, Data, HS, VS, AVID, FID) are either tristated or inputs on power on reset. Hence, i configured the control registers for these...
    on Aug 4, 2010

  • Forum Post: Re: Vertical & Horizontal Sync Loss - TVP5147PFP

    Sornam Viswanathan V
    Hello Larry, Here is another update. I guess i made a mistake when i said that i was getting a stable Hsync and Vsync out with the registers indicating lost lock. I read the registers immediately after power up and did not read the registers again. But the registers do indicate that horizontal...
    on Aug 11, 2010

  • Forum Post: Re: help for -> major area of digital video into several sub-divided parts.

    Larry Taylor
    Jamal, You may want to look at some of the DM video processors such as the DM6467. These parts are used with anlog front-ends such as the TVP7002 (HD component and graphics support) an TVP5146/7 video decoders (SDTV and composite video support). HDMI can also be supported. EVM schematics should be...
    on Jan 11, 2011

  • Forum Post: TVP5147 grayscale combing

    Andrew Leech (medmont)
    Hello, I'm replacing a legacy PCI video capture card (Leutron brand) with a custom USB video capture unit using a TVP5147PFP. I realise this part is now NRND but originally thought I had to stick with it for square pixel support. I now see that a patch for TVP5147M enables square pixel support...
    on Feb 11, 2011

  • Forum Post: Re: TVP5147 grayscale combing

    Larry Taylor
    Hi Andrew, Can you porvide a picture of the grayscale test pattern that you are using? Does this occur for only certain types of test paterns? Are you using an anti-alias filter on the TVP video input?
    on Feb 11, 2011

  • Forum Post: Re: TVP5147 grayscale combing

    Andrew Leech66752
    Hi Larry, I'm away from work for the weekend already (in Australia), you probably are too by now. Either way I don't have a copy of a test pattern, as I was just feeding in the signal from a PAL/CCID B/W camera. Moving the camera around obviously changes the overall shape of the histograms...
    on Feb 12, 2011

  • Forum Post: Re: TVP5147 grayscale combing

    Andrew Leech (medmont)
    I got some TVP5147M1's to try, turns out they've got exactly the same combing effect, no visible change. On a related note, patch 7.02.00 adds perfectly functional square pixel support, which is completely compatible with me existing code which is great. Do you know why then, that in 7.03...
    on Feb 23, 2011

  • Forum Post: Re: question on configuration of TVP5147

    James Nave
    Vaishnavi, You have the correct register settings for 20-bit mode. Not sure what's causing the problem. Are using the TVP5147 or TVP5147M1? Which patch are you using? Do you have a pull-down resistor on pin 69? Regards, Jim
    on Mar 23, 2011

  • Forum Post: Re: question on configuration of TVP5147

    James Nave
    Vaishnavi, To select 16-bit mode, you should only need to write 41h to register 33h. Please check bit 3 of register 3Ah to verify that the C-PLL is locked to the color subcarrier. Please check bit 3 of register 3Bh to verify that color killer is not active. If so, write 60h to register 05h to...
    on Mar 24, 2011

  • Forum Post: TVP5147M1 output CLK

    honghui zhang
    Hello, I am using TVP5147M1 output decoded video data and CLK, the input to the SN65LV1023 transmitted through the CPLD to the fiber, but seems to be TVP5147M1 output clock jitter is too large, the SN65LV1224 receiver bit error rate is relatively high, is there There is no way to solve? Then I made...
    on Jul 27, 2011

  • Forum Post: Re: TVP5147M1 output CLK

    James Nave
    Hello Honghui, The TVP5147M1 H-PLL generates a line-locked clock output rather than a fixed-frequency clock output. Thus, the output clock frequency will track variations in the input horizontal frequency (a.k.a. line rate). This frequency variation can be problematic in parallel to serial applications...
    on Jul 28, 2011

  • Forum Post: Re: TVP5147M1 output CLK

    honghui zhang
    Hi Jim, I think it should be TVP5147M1 output clock jitter caused, there is no way to reduce or remove the jitter on the clock? Regards, Honghui
    on Jul 30, 2011

  • Forum Post: Re: TVP5147M1 output CLK

    James Nave
    Hello Honghui, Recommend setting the TVP5147M1 H-PLL to its slowest setting by writing 30h to register 03h. If that doesn't work, you may need to consider using an external FIFO to convert from a line-locked clock to a fixed-frequency clock. The TVP5158 4-Ch video decoder supports this feature...
    on Aug 2, 2011

  • Forum Post: Re: TVP5147M1 output CLK

    honghui zhang
    Hi Jim, I tried to TVP5147M1 the H-PLL open, but to no avail. If, as you said the increase in FIFO, FIFO write clock I can TVP5147M1 the DATACLK, but how to generate FIFO read clock? Because the clock read and write clock synchronization needs, need to use digital phase-locked loop? FIFO read clock...
    on Aug 4, 2011

  • Forum Post: Re: TVP5147M1 output CLK

    James Nave
    Hello Honghui, Are you using the older SN65LV1023 and SN65LV1224 devices or the newer SN65LV1023A and SN65LV1224B devices? The SN65LV1023 and SN65LV1224 devices are not recommended for new designs and are only specified for 30MHz to 66MHz operation. If so, this would be an issue since the TVP5147M1...
    on Aug 4, 2011

  • Forum Post: TVP5147 - Multiple decoders on same bus?

    jc-ti
    Are there any special hardware considerations when connecting two TVP5147's on the same bus? It looks like from the datasheet that once they are out of reset, only the INTREQ signal is driven. If the INTREQ is not used, is it safe to connect other pins on the same bus without any switches or multiplexors...
    on Sep 16, 2011

  • Forum Post: Re: TVP5147 - Multiple decoders on same bus?

    James Nave
    Jeff, Yes, clock and data outputs of two TVP5147s can share the same bus as long as only one device is enabled at a time. Regards, Jim
    on Sep 19, 2011

  • Forum Post: Re: TVP5147 - Multiple decoders on same bus?

    jc-ti
    Thanks for the response. I saw in the datasheet that the DATACLK pin is set to "OUTPUT" during reset. Does this mean it is actively driving high or low during this time? If so, is it high or low? Jeff
    on Sep 19, 2011

  • Forum Post: Re: TVP5147 - Multiple decoders on same bus?

    James Nave
    Jeff, The TVP5147M1 outputs a clock around 26MHz during reset. Therefore, the two devices should not be reset at the same time when sharing the same bus. Also, the DATACLK output state is not specified during the time interval after initial power up and before reset. Therefore, it might be easier...
    on Sep 20, 2011
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