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Hello experts,

I'm trying to maneuver between many rocks and hard places in this one:

Here is my setup:

• Version: 5.1.0.09000
• uia_1_00_03_25
• bios_6_33_00_19
• ipc_1_23_05_40
• C6000 Code Generation Tools 7.3.2
• COFF ABI
• Device: C6424

Since the C6424 device does not support hardware profiling/trace, we are having to resort to the Simulator (Megamodule / little-endian / ti.platforms.evm6424).

Our goal is to run the entire system - RTOS and all (as large a subset as possible) in the Simulator. I have done this earlier for a C6472-based system with good results and elsewhere in elaborate ARM-based co-design environments...

# To that effect we are simulating I/O using PIN-connect and faux-HWIs. The simulator FAQ (http://processors.wiki.ti.com/index.php/Simulator_FAQ) seems unclear (spru600i.pdf) about the support for McBSP in C6424-sim. PLEASE CLARIFY.

# PLEASE CLARIFY on the ability to model and simulate external memory (DDR) width (16 vs 32) and timings

# The Cache Layout Tool workflow (http://processors.wiki.ti.com/index.php/Program_Cache_Layout)

• seems to work for simple/linear main-programs that run to completion - in that it dumps the .PDAT file out when it exits ex: (http://processors.wiki.ti.com/index.php/Tech:CLT_Tutor_Sources) - can you send me the real project/linkermaps for this?
• I haven't managed to dump .PDAT  for BIOS-style apps that run/idle without exiting (I thought there was a symbol exposed by the RTS to dump data... but cannot seem to find it). PLEASE CLARIFY.
• Setting up the Profiler and collecting data in the Sim seems to work... the problem is if "DATA->Export All/Selected" the only way to get this out? Can this be used to feed the rest of the Cache-Layout-Optimization flow? PLEASE CLARIFY.

Thanks!