Part Number: UCD3138
Tool/software: TI C/C++ Compiler
I am using CCS6.1 with compiler 5.22. I found the result of multiplication of two 32-bits data is not correct. I defined the result as 64 bits data. the correct result should be 0x0000 0056 0038 7512. I saw one register R0 has the number 0x0000 0056, another register R1 has the number 0x00387512, which is correct. however, the result I get is 0x0038 7512 0000 0056, which seems the two registers's data are put in the wrong order.
Is it a bug or I didn't configure the CCS correctly?
In reply to Chester Gillon:
In reply to Julie Zhu:
I was able to create a small test case using lab 1 of the UCD3138 training labs firmware package and could verify that both CCSv7.1.0 (Windows) and CCSv6.2.0 (Ubuntu 16.04/64) work fine.
I am using my UCD3138OL64EVM-031 with a Spectrum Digital XDS200 USB JTAG debug probe.
Therefore I would simply update your copy of CCS to benefit from this bug.
Hope this helps,
In reply to desouza:
desouzaI was able to create a small test case using lab 1 of the UCD3138 training labs firmware package and could verify that both CCSv7.1.0 (Windows) and CCSv6.2.0 (Ubuntu 16.04/64) work fine
Whereas the problem Julie reported was that a 64-bit variable which the compiler optimizer had placed in a pair of 32-bit variables was displayed incorrectly, while a 64-bit global variable was displayed correctly.
Are you able to re-check with a UCD3138 example which has optimization level of one (or greater) that CCS v6.2.0 or v7.1.0 correctly display a 64-bit variable held in a register pair?
It may require some experimentation, but I found with the following code fragment compiled at optimization level one caused the sum 64-bit variable to be stored in a register pair, while the 64-bit scale_product variable was optimized out of the debug information:
uint32_t x = 0x8a2290;
uint32_t y = 0xa000;
sum = 0;
for (iteration = 0; iteration < 5; iteration++)
scale_product = (uint64_t) x * y;
printf ("0x%x * 0x%x = 0x%llx\n", x, y, scale_product);
sum += scale_product;
Good point; I tried several things but couldn't find a way for the compiler to place the 64-bit result in a register pair in my system here.
In search of a possible outstanding bug, I found SDSCM00008685 at the file below:
Given this is still an outstanding bug even on modern ARM compiler releases, there is a chance the debug team implemented the workaround proposed there: arbitrarily pointing the two halves of the variable at Rn:Rn+1 and placing them on the Variables/Expressions Views. As hinted above, the fact this ARM7 is a big endian platform, it may be possible the workaround fails as the data could have been stored in reverse order.
I searched around in our bug system for any fixes to the debugger and the closest ones I could find are SDSCM00039488 and SDSCM00042523 - both marked and confirmed as fixed. However, the testcases were targeted for other architectures.
At this point I would need a complete testcase to try to fully reproduce this in this platform. I can't confirm if this is still outstanding in our newest IDEs.
desouzaAt this point I would need a complete testcase to try to fully reproduce this in this platform.
The program was tested on a number of CCS and TI ARM compiler releases.
1) CCS 7.1.0.00016 and compiler v5.2.5:
In this combination the location for the 64-bit variable sum is reported as the single "Register R5" and the value is incorrectly shown as 0x559A000000000056" instead of the expected "0x00000056559A0000".
2) CCS 7.1.0.00016 and compiler v16.9.3.LTS:
In the combination the location for the 64-bit variable a pair of 32-bit registers "R7:32,R5:32" and the value is correctly shown as "0x00000056559A0000".
3) CCS 6.1.3.00033 and compiler v5.2.5:
4) CCS 6.1.3.00033 and compiler v16.9.3.LTS:
In this combination the CCS debugger reports an error the register for the 64-bit variable is unknown.
The conclusions are:
a) CCS 7.1.0.00016 (as well as CCS 6.1.3.00033) display the value of a 64-bit variable in a register pair incorrectly, such that the upper and lower 32-bit words are swapped, when used with a TI ARM compiler which only describes the 64-bit variable as in a 32-bit register and the ARM device is big-endian.
b) Somewhere between the TI ARM compilers v5.2.5 and v16.9.3.LTS there has been a change to describe the location of a 64-bit variable as a register pair which allows the CCS debugger to display the 64-bit variable held in a pair of registers on a ARM big-endian device correctly. However, the new debug information is not understood by older CCS versions. Don't know which CCS version between 6.1.3 and 7.1 in which the change to understand the debug information changed.
desouzaI found out that CCSv7.1.0 + CGT 15.12.5 shows the issue while, as you saw, 16.9.3 does not.
With v16.9.1.LTS a register pair is reported at the location:
;* V2 assigned to sum
$C$DW$7 .dwtag DW_TAG_variable
.dwattr $C$DW$7, DW_AT_name("sum")
.dwattr $C$DW$7, DW_AT_TI_symbol_name("sum")
.dwattr $C$DW$7, DW_AT_type(*$C$DW$T$71)
.dwattr $C$DW$7, DW_AT_location[DW_OP_reg5 DW_OP_piece 4 DW_OP_reg7 DW_OP_piece 4]
With v15.12.5.LTS only a single register is reported as the location:
;* V2 assigned to sum
$C$DW$8 .dwtag DW_TAG_variable
.dwattr $C$DW$8, DW_AT_name("sum")
.dwattr $C$DW$8, DW_AT_TI_symbol_name("sum")
.dwattr $C$DW$8, DW_AT_type(*$C$DW$T$71)
.dwattr $C$DW$8, DW_AT_location[DW_OP_reg5]
Where the type of sum is 64-bits via the $C$DW$T$71 type:
$C$DW$T$71 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$71, DW_AT_name("uint64_t")
.dwattr $C$DW$T$71, DW_AT_type(*$C$DW$T$15)
.dwattr $C$DW$T$71, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$71, DW_AT_decl_file("C:/ti_ccs7_1/ccsv7/tools/compiler/ti-cgt-arm_15.12.5.LTS/include/stdint.h")
.dwattr $C$DW$T$71, DW_AT_decl_line(0x33)
.dwattr $C$DW$T$71, DW_AT_decl_column(0x20)
Therefore, between the v15.12.x and v16.9.x series compilers there has been an enhancement to the debug information to allow a 64-bit variable held in a register to be given the location of a register pair.
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