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error: Ensure the linker command file matches the memory map on Sitara AM389
I'm trying to flash my NAND memory on custom board with Sitara AM389 processor on it. NAND has 8bit data lines. I followed these steps http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_PSP_Flashing_Tools_Guide#Starting_CCS but I'm having a error when I load nand-flash-writer.out file to processor.
I'm getting this error message in CCS4:
CortexA8: File Loader: Data verification failed at address 0x80000000 Please verify target memory and memory map.Error found during data verification.Ensure the linker command file matches the memory map.CortexA8: Unable to terminate memory download: NULL buffer pointer at 0x3a9f
Can somebody help my with this problem and give some tip what could be the problem? It seems that NAND chip is ok, because from u-boot I can see that it recognized.
That error occurs when CCS has attempted to write to a location and has read back the value from the device to confirm that it was written correctly and found that it was not.
0x8000000 is external memory (DDR Bank 0)
I believe that the DDR has not been initialized. That wiki topic for flashing has a section on loading the GEL file to initialize the DDR. Did you follow those steps?
If my reply answers your question please mark the thread as answered
yes I did follow those step for loading GEL files and I've executed scripts Scripts -> NETRA External Memory -> do_all. After they finish I get the valid CCS console message! So DDR memories are initialised. To verify that my DDR memories are ok, I've already managed to execute DDR3 software levelling process http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init. So I think this isn't a issue.
What happens if you open a memory view and try to write to 0x8000000
after I try to write at memory location 0x8000000 I get this console message:
CortexA8: Warning: (Error -1065 @ 0x3D5A) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Release 5.0.333.0)
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