• State Resolved
  • Locked Locked
  • Replies 11 replies
  • Subscribers 54 subscribers
  • Views 4799 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Halting AM335x after system reset command (Wait-In-Reset)

Vasili Galka
Expert 2690 points

Hi,

How can I configure CCS so that my AM335x device enters the Wait-In-Reset state when issuing "System Reset" command?

Best,
Vasili

  • 0
    TI__Intellectual 760 points

    Vasili, 

    You can enable "wait-in-reset" by selecting menu item Run -> Advanced -> enable halt on reset. 

    The Wait-In-Reset can also be activated by setting EMU0 pin to low and EMU1 pin to high at the chip boundary during device power on reset. 

    Ning

  • 0 in reply to Ning Kang
    Guru 19835 points

    Hi Ning,

    To generate the system reset when "System Reset" command is issued, is SRST/SYSRST# pin needed?

    To enable the wait-in-reset when "enable halt on reset" is selected, are EMU[1:0] pins needed?

    If these pins are not implemented, can these capability be performed via ICEPick to AM335x?

    Best regards,

    Daisuke

     

  • 0 in reply to Ning Kang
    Guru 19835 points

    Hi Ning,

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Intellectual 760 points

    Daisuke, 

    The "system reset" feature in CCS goes through directly to the ICEPick logic inside the device. This does not require any external pins such as SRST. The reset is functional equivalent of toggling the physical pin. 

    Similarly, "halt-on-reset" programs the registers directly, which does not require EMU pins. 

    Regards,

    Ning

  • 0 in reply to Ning Kang
    Guru 19835 points

    Hi Ning,

    Thank you for your reply.

    If these pins are implemented, can the pins be controlled by CCS?

    Is SRST/SYSRST# pin also asserted when "System Reset" command is issued?

    EMU[1:0] pins seem to be configured in a target configuration file. What do these configure?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Intellectual 760 points

    Daisuke, 

    No, the SRST/SYSRST# pin is not asserted by "system reset" command. 

    The EMU[1:0] pins is another way to activate the Wait-In-Reset mode. Once set in target configuration, the device will get into Wait-In-Reset mode after Power On Reset of the device. 

    Regards,

    Ning

  • 0 in reply to Ning Kang
    Guru 19835 points

    Hi Ning,

    Thank you for your reply.

    Ning Kang said:

    No, the SRST/SYSRST# pin is not asserted by "system reset" command.

    Does the "System Reset" command simulate the Power On Reset, or the Warm Reset?

    Ning Kang said:

    The EMU[1:0] pins is another way to activate the Wait-In-Reset mode. Once set in target configuration, the device will get into Wait-In-Reset mode after Power On Reset of the device.

    Do you explain the "The Power-On-Reset Boot-Mode" in target configuration?

    What is "The JTAG nTRST Boot-Mode" in target configuration? Can this be used for the AM335x?

    Best regards,

    Daisuke

     

  • 0 in reply to Ning Kang
    Guru 19835 points

    Hi Ning,

    I encounter the error in the GEL initialization after the "System Reset" command was issued with selecting the "Enable Halt On Reset".

    Please tell me how to remove the error such as follows.

    ////////////////////////////////////////////////////////////

    CortxA8: Trouble Reading Memory Block at 0x44e10040 on Page 0 of Length 0x4: (Error -1205 @ 0x44E10040) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.232.0)
    AM335x_Beaglebone_Initialization() cannot be evaluated.
    Target failed to read 0x44E10040
     at (*((unsigned int *) (0x44E10000+0x40))>>22) [beaglebone.gel:360]
     at GetInputClockFrequency() [beaglebone.gel:431]
     at ARM_OPP100_Config() [beaglebone.gel:351]
     at AM335x_Beaglebone_Initialization()

    ////////////////////////////////////////////////////////////

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Intellectual 760 points
    Daisuke, These errors are from the GEL function that fail to access the memory address as specified in the error message. This could happen for a couple of reasons: 1. the memory region is not accessable after reset. You may also try to hit the reset button on the board or toggle the reset signal at the device boundary to see if yo are getting the same error messages. 2. the halt-on-reset will halt the CPU at the reset vector before running the entire boot code. If the boot code have some certain initialization routine such as memory initialization, enabling clock and power domains, the access in the Gel function may fail. You may comment out the OnTargetConnect() function to avoid these errors. But the device may not be initialized properly or at least the same way as before. Regards, Ning
  • 0 in reply to Ning Kang
    Guru 19835 points

    Hi Ning,

    Thank you for your reply. Sorry for my late reply.

    Best regards,

    Daisuke